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ath5k: Increase PHY settling parameters for turo mode
* On turbo mode increase PHY settling times, note that we only increase switch settling time on AR5212 as indicated by initvals. * A few cleanups: Move frame control settings for AR5210 from reset_tx_queue to tweak_initvals and remove phy_scal settings from tweak_initvals (we tweak them alread on set_sleep_clock). Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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325089ab58
commit
b405086ba4
4 changed files with 52 additions and 29 deletions
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@ -259,15 +259,23 @@
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#define AR5K_INIT_TX_LAT_BG 384
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/* Tx latency for 40MHz (turbo) operation (min ?) */
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#define AR5K_INIT_TX_LAT_MIN 32
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/* Default Tx/Rx latencies (same for 5211)*/
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#define AR5K_INIT_TX_LATENCY_5210 54
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#define AR5K_INIT_RX_LATENCY_5210 29
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/* Tx frame to Tx data start delay */
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#define AR5K_INIT_TXF2TXD_START_DEFAULT 14
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#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
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#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
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/* Default Tx/Rx latencies (same for 5211)*/
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#define AR5K_INIT_TX_LATENCY_5210 54
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#define AR5K_INIT_RX_LATENCY_5210 29
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/* We need to increase PHY switch and agc settling time
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* on turbo mode */
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#define AR5K_SWITCH_SETTLING 5760
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#define AR5K_SWITCH_SETTLING_TURBO 7168
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#define AR5K_AGC_SETTLING 28
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/* 38 on 5210 but shouldn't matter */
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#define AR5K_AGC_SETTLING_TURBO 37
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/* GENERIC CHIPSET DEFINITIONS */
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@ -271,19 +271,6 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
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ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ?
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AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
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AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
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/* Set AR5K_PHY_SETTLING */
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ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ?
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(ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
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| 0x38 :
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(ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
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| 0x1C,
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AR5K_PHY_SETTLING);
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/* Set Frame Control Register */
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ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ?
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(AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
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AR5K_PHY_TURBO_SHORT | 0x2020) :
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(AR5K_PHY_FRAME_CTL_INI | 0x1020),
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AR5K_PHY_FRAME_CTL_5210);
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}
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/*
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@ -2245,6 +2245,8 @@
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#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
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AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
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/*---[5111+]---*/
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#define AR5K_PHY_FRAME_CTL_WIN_LEN 0x00000003 /* Force window length (?) */
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#define AR5K_PHY_FRAME_CTL_WIN_LEN_S 0
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#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
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#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
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#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */
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@ -688,19 +688,6 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
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AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
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AR5K_TXCFG_DCU_DBL_BUF_DIS);
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/* Set DAC/ADC delays */
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if (ah->ah_version == AR5K_AR5212) {
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u32 scal;
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struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
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scal = AR5K_PHY_SCAL_32MHZ_2417;
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else if (ee->ee_is_hb63)
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scal = AR5K_PHY_SCAL_32MHZ_HB63;
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else
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scal = AR5K_PHY_SCAL_32MHZ;
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ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
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}
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/* Set fast ADC */
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if ((ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
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@ -740,6 +727,45 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
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AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
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AR5K_DIAG_SW_ECO_ENABLE);
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}
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if (ah->ah_bwmode) {
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/* Increase PHY switch and AGC settling time
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* on turbo mode (ath5k_hw_commit_eeprom_settings
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* will override settling time if available) */
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if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
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AR5K_PHY_SETTLING_AGC,
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AR5K_AGC_SETTLING_TURBO);
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/* XXX: Initvals indicate we only increase
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* switch time on AR5212, 5211 and 5210
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* only change agc time (bug?) */
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if (ah->ah_version == AR5K_AR5212)
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
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AR5K_PHY_SETTLING_SWITCH,
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AR5K_SWITCH_SETTLING_TURBO);
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if (ah->ah_version == AR5K_AR5210) {
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/* Set Frame Control Register */
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ath5k_hw_reg_write(ah,
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(AR5K_PHY_FRAME_CTL_INI |
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AR5K_PHY_TURBO_MODE |
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AR5K_PHY_TURBO_SHORT | 0x2020),
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AR5K_PHY_FRAME_CTL_5210);
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}
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/* On 5413 PHY force window length for half/quarter rate*/
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} else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
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(ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
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AR5K_PHY_FRAME_CTL_WIN_LEN,
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3);
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}
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} else if (ah->ah_version == AR5K_AR5210) {
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/* Set Frame Control Register for normal operation */
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ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
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AR5K_PHY_FRAME_CTL_5210);
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}
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}
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static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
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