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PCI: mvebu: move clock enable before register access
The clock passed to PCI controller found on MVEBU SoCs may come from a clock gate. This requires the clock to be enabled before any registers are accessed. Therefore, move the clock enable before register iomap to ensure it is enabled. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
parent
5b4deb6526
commit
b42285f66f
1 changed files with 12 additions and 13 deletions
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@ -897,11 +897,23 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
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continue;
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continue;
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}
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}
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port->clk = of_clk_get_by_name(child, NULL);
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if (IS_ERR(port->clk)) {
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dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
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port->port, port->lane);
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continue;
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}
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ret = clk_prepare_enable(port->clk);
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if (ret)
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continue;
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port->base = mvebu_pcie_map_registers(pdev, child, port);
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port->base = mvebu_pcie_map_registers(pdev, child, port);
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if (IS_ERR(port->base)) {
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if (IS_ERR(port->base)) {
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dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
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dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
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port->port, port->lane);
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port->port, port->lane);
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port->base = NULL;
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port->base = NULL;
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clk_disable_unprepare(port->clk);
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continue;
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continue;
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}
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}
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@ -917,22 +929,9 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
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port->port, port->lane);
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port->port, port->lane);
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}
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}
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port->clk = of_clk_get_by_name(child, NULL);
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if (IS_ERR(port->clk)) {
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dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
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port->port, port->lane);
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iounmap(port->base);
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port->haslink = 0;
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continue;
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}
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port->dn = child;
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port->dn = child;
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clk_prepare_enable(port->clk);
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spin_lock_init(&port->conf_lock);
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spin_lock_init(&port->conf_lock);
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mvebu_sw_pci_bridge_init(port);
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mvebu_sw_pci_bridge_init(port);
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i++;
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i++;
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}
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}
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