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OMAP: DSS2: HDMI: change regn definition
regn divider is currently programmed to the registers without change, but when calculating clock frequencies it is used as regn+1. To make this similar to how DSI handles the dividers this patch changes the regn value to be used as such for calculations, but the value programmed to registers is regn-1. This simplifies the clock frequency calculations, makes it similar to DSI, and also allows us to use regn value 0 as undefined. Cc: Mythri P K <mythripk@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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8d88767a43
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3 changed files with 5 additions and 4 deletions
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@ -60,7 +60,7 @@
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#define OMAP_HDMI_TIMINGS_NB 34
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#define OMAP_HDMI_TIMINGS_NB 34
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#define HDMI_DEFAULT_REGN 15
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#define HDMI_DEFAULT_REGN 16
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#define HDMI_DEFAULT_REGM2 1
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#define HDMI_DEFAULT_REGM2 1
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static struct {
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static struct {
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@ -426,7 +426,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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else
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else
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pi->regn = dssdev->clocks.hdmi.regn;
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pi->regn = dssdev->clocks.hdmi.regn;
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refclk = clkin / (pi->regn + 1);
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refclk = clkin / pi->regn;
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/*
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/*
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* multiplier is pixel_clk/ref_clk
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* multiplier is pixel_clk/ref_clk
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@ -452,7 +452,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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* is greater than 1000MHz
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* is greater than 1000MHz
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*/
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*/
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pi->dcofreq = phy > 1000 * 100;
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pi->dcofreq = phy > 1000 * 100;
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pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
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pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
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/* Set the reference clock to sysclk reference */
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/* Set the reference clock to sysclk reference */
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pi->refsel = HDMI_REFSEL_SYSCLK;
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pi->refsel = HDMI_REFSEL_SYSCLK;
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@ -92,7 +92,7 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
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r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
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r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
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r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
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r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
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r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
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r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
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hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
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hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
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@ -520,6 +520,7 @@ struct omap_dss_device {
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} dsi;
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} dsi;
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struct {
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struct {
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/* regn is one greater than TRM's REGN value */
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u16 regn;
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u16 regn;
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u16 regm2;
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u16 regm2;
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} hdmi;
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} hdmi;
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