MMC core:
- Fix broken cache-flush support for Micron eMMCs - Revert "mmc: core: Capture correct oemid-bits for eMMC cards" MMC host: - sdhci_am654: Fix TAP value parsing for legacy speed mode - sdhci-pci-gli: Fix support for ASPM mode for GL9755/GL9750 - vub300: Fix an error path in probe -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAmVOIL8XHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCnv6w/9FxD7hl2XBeHEoiLnzB3lX4YO zcsn3cpOCBjJnslOsBwRxk+07YK18umCZIWBSeN6PnN2MXjacvPJHiMvdyX5N/4x QvxxKhC0k9vyuNAHMSk3myKNSIYcXm3xz1iLYesYnfPDOMRFZsN4LgWnYamgYfA6 cRooF3zSN8mY7ftTn6z0YTH7vUTA6m91qE2LpEDeCfOIcXRRG3diZ3VbKef5ugXw XdvfaQ0lZUvXxlNSQa+ZgtgIKmTbj8OOD0ZBsEfj+CgsFFe2D1EDQ665Zqtw9RDa 8Vq1RDzan4EbxJetPIkppGPPpQIxJQtRvo45aDxP4DaDxZcrPblVsTgPPSxO9q37 4m9q3dTabJZmVC1UehjTEGwHakf50S6S/seCjKvGVn9jPMY82uuOm/MdUzwik1cl Os0MPviSatJ/A1tVIDCVSX+Xn6RZOn0a3jjQ1fESyS+/65hXe82I8IFXT+ZM6ZK+ 2RBkfAfs6lfSY3LRCtMKgQDLBvYe83qRe91zD/0eqTDOY9396BoHZLdYvX8uP7Ah sBrFRvPkNSMktBth7WNEetU6l1VH6b/8PuoOBswKA+820Jm/3kvAS34bTce/WzPP QN5zgD1SchUO6qPH9dh1AdG1awXLev4+dxYhKZEMFbi8sVqXekVIb2Sh66D+FBJu svZrEpAg3KgAJALsjZQ= =EohY -----END PGP SIGNATURE----- Merge tag 'mmc-v6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "MMC core: - Fix broken cache-flush support for Micron eMMCs - Revert 'mmc: core: Capture correct oemid-bits for eMMC cards' MMC host: - sdhci_am654: Fix TAP value parsing for legacy speed mode - sdhci-pci-gli: Fix support for ASPM mode for GL9755/GL9750 - vub300: Fix an error path in probe" * tag 'mmc-v6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER mmc: sdhci-pci-gli: GL9755: Mask the replay timer timeout of AER Revert "mmc: core: Capture correct oemid-bits for eMMC cards" mmc: vub300: fix an error code mmc: Add quirk MMC_QUIRK_BROKEN_CACHE_FLUSH for Micron eMMC Q2J54A mmc: sdhci_am654: fix start loop index for TAP value parsing
This commit is contained in:
commit
b456259e15
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@ -2381,8 +2381,10 @@ enum mmc_issued mmc_blk_mq_issue_rq(struct mmc_queue *mq, struct request *req)
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}
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}
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ret = mmc_blk_cqe_issue_flush(mq, req);
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ret = mmc_blk_cqe_issue_flush(mq, req);
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break;
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break;
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case REQ_OP_READ:
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case REQ_OP_WRITE:
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case REQ_OP_WRITE:
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card->written_flag = true;
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fallthrough;
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case REQ_OP_READ:
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if (host->cqe_enabled)
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if (host->cqe_enabled)
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ret = mmc_blk_cqe_issue_rw_rq(mq, req);
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ret = mmc_blk_cqe_issue_rw_rq(mq, req);
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else
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else
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@ -280,4 +280,8 @@ static inline int mmc_card_broken_sd_cache(const struct mmc_card *c)
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return c->quirks & MMC_QUIRK_BROKEN_SD_CACHE;
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return c->quirks & MMC_QUIRK_BROKEN_SD_CACHE;
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}
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}
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static inline int mmc_card_broken_cache_flush(const struct mmc_card *c)
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{
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return c->quirks & MMC_QUIRK_BROKEN_CACHE_FLUSH;
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}
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#endif
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#endif
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@ -104,7 +104,7 @@ static int mmc_decode_cid(struct mmc_card *card)
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case 3: /* MMC v3.1 - v3.3 */
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case 3: /* MMC v3.1 - v3.3 */
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case 4: /* MMC v4 */
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case 4: /* MMC v4 */
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card->cid.manfid = UNSTUFF_BITS(resp, 120, 8);
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card->cid.manfid = UNSTUFF_BITS(resp, 120, 8);
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card->cid.oemid = UNSTUFF_BITS(resp, 104, 8);
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card->cid.oemid = UNSTUFF_BITS(resp, 104, 16);
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card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8);
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card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8);
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card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8);
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card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8);
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card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8);
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card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8);
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@ -2086,13 +2086,17 @@ static int _mmc_flush_cache(struct mmc_host *host)
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{
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{
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int err = 0;
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int err = 0;
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if (mmc_card_broken_cache_flush(host->card) && !host->card->written_flag)
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return 0;
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if (_mmc_cache_enabled(host)) {
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if (_mmc_cache_enabled(host)) {
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err = mmc_switch(host->card, EXT_CSD_CMD_SET_NORMAL,
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err = mmc_switch(host->card, EXT_CSD_CMD_SET_NORMAL,
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EXT_CSD_FLUSH_CACHE, 1,
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EXT_CSD_FLUSH_CACHE, 1,
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CACHE_FLUSH_TIMEOUT_MS);
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CACHE_FLUSH_TIMEOUT_MS);
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if (err)
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if (err)
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pr_err("%s: cache flush error %d\n",
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pr_err("%s: cache flush error %d\n", mmc_hostname(host), err);
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mmc_hostname(host), err);
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else
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host->card->written_flag = false;
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}
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}
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return err;
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return err;
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@ -110,11 +110,12 @@ static const struct mmc_fixup __maybe_unused mmc_blk_fixups[] = {
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MMC_QUIRK_TRIM_BROKEN),
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MMC_QUIRK_TRIM_BROKEN),
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/*
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/*
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* Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to
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* Micron MTFC4GACAJCN-1M supports TRIM but does not appear to support
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* support being used to offload WRITE_ZEROES.
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* WRITE_ZEROES offloading. It also supports caching, but the cache can
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* only be flushed after a write has occurred.
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*/
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*/
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MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc,
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MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc,
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MMC_QUIRK_TRIM_BROKEN),
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MMC_QUIRK_TRIM_BROKEN | MMC_QUIRK_BROKEN_CACHE_FLUSH),
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/*
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/*
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* Kingston EMMC04G-M627 advertises TRIM but it does not seems to
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* Kingston EMMC04G-M627 advertises TRIM but it does not seems to
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@ -28,6 +28,9 @@
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#define PCI_GLI_9750_PM_CTRL 0xFC
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#define PCI_GLI_9750_PM_CTRL 0xFC
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#define PCI_GLI_9750_PM_STATE GENMASK(1, 0)
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#define PCI_GLI_9750_PM_STATE GENMASK(1, 0)
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#define PCI_GLI_9750_CORRERR_MASK 0x214
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#define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
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#define SDHCI_GLI_9750_CFG2 0x848
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#define SDHCI_GLI_9750_CFG2 0x848
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#define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
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#define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
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#define GLI_9750_CFG2_L1DLY_VALUE 0x1F
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#define GLI_9750_CFG2_L1DLY_VALUE 0x1F
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@ -152,6 +155,9 @@
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#define PCI_GLI_9755_PM_CTRL 0xFC
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#define PCI_GLI_9755_PM_CTRL 0xFC
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#define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
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#define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
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#define PCI_GLI_9755_CORRERR_MASK 0x214
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#define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
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#define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
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#define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
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#define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
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#define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
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@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host *host)
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value &= ~PCI_GLI_9750_PM_STATE;
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value &= ~PCI_GLI_9750_PM_STATE;
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pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
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pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
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/* mask the replay timer timeout of AER */
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pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
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value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
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pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
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gl9750_wt_off(host);
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gl9750_wt_off(host);
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}
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}
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@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
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value &= ~PCI_GLI_9755_PM_STATE;
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value &= ~PCI_GLI_9755_PM_STATE;
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pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
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pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
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/* mask the replay timer timeout of AER */
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pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
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value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
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pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
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gl9755_wt_off(pdev);
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gl9755_wt_off(pdev);
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}
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}
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@ -598,7 +598,7 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
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return 0;
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return 0;
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}
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}
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for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
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for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
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ret = device_property_read_u32(dev, td[i].otap_binding,
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ret = device_property_read_u32(dev, td[i].otap_binding,
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&sdhci_am654->otap_del_sel[i]);
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&sdhci_am654->otap_del_sel[i]);
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@ -2309,6 +2309,7 @@ static int vub300_probe(struct usb_interface *interface,
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vub300->read_only =
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vub300->read_only =
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(0x0010 & vub300->system_port_status.port_flags) ? 1 : 0;
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(0x0010 & vub300->system_port_status.port_flags) ? 1 : 0;
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} else {
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} else {
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retval = -EINVAL;
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goto error5;
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goto error5;
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}
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}
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usb_set_intfdata(interface, vub300);
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usb_set_intfdata(interface, vub300);
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@ -295,7 +295,9 @@ struct mmc_card {
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#define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */
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#define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */
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#define MMC_QUIRK_BROKEN_SD_DISCARD (1<<14) /* Disable broken SD discard support */
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#define MMC_QUIRK_BROKEN_SD_DISCARD (1<<14) /* Disable broken SD discard support */
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#define MMC_QUIRK_BROKEN_SD_CACHE (1<<15) /* Disable broken SD cache support */
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#define MMC_QUIRK_BROKEN_SD_CACHE (1<<15) /* Disable broken SD cache support */
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#define MMC_QUIRK_BROKEN_CACHE_FLUSH (1<<16) /* Don't flush cache until the write has occurred */
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bool written_flag; /* Indicates eMMC has been written since power on */
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bool reenable_cmdq; /* Re-enable Command Queue */
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bool reenable_cmdq; /* Re-enable Command Queue */
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unsigned int erase_size; /* erase size in sectors */
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unsigned int erase_size; /* erase size in sectors */
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Loading…
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