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drm/amdgpu: Add graphics cache rinse packet for sdma
Add emit mem sync callback for sdma_v5_2 In amdgpu sync object test, three threads created jobs to send GFX IB and SDMA IB in sequence. After the first GFX thread joined, sometimes the third thread will reuse the same physical page to store the SDMA IB. There will be a risk that SDMA will read GFX IB in the previous physical page. So it's better to flush the cache before commit sdma IB. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 28 additions and 0 deletions
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@ -369,6 +369,33 @@ static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
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}
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/**
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* sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
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*
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* @ring: amdgpu ring pointer
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* @job: job to retrieve vmid from
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* @ib: IB object to schedule
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*
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* flush the IB by graphics cache rinse.
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*/
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static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
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{
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uint32_t gcr_cntl =
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SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
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SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
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SDMA_GCR_GLI_INV(1);
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/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
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amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
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amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
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amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
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SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
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amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
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SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
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amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
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SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
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}
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/**
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* sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
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*
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@ -1663,6 +1690,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
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10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
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.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
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.emit_ib = sdma_v5_2_ring_emit_ib,
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.emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
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.emit_fence = sdma_v5_2_ring_emit_fence,
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.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
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.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
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