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drm/amdgpu: Use dynamic IP offset for register access on SOC15
Update the register access macros and functions to take into account the new dynamic IP base offsets. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Shaoyun Liu
Alex Deucher
parent
4522824c48
commit
b466107e8b
2 changed files with 65 additions and 95 deletions
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@ -107,23 +107,11 @@ static const u32 golden_settings_sdma_rv1[] =
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SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
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};
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static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
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static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
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u32 instance, u32 offset)
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{
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u32 base = 0;
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switch (instance) {
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case 0:
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base = SDMA0_BASE.instance[0].segment[0];
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break;
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case 1:
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base = SDMA1_BASE.instance[0].segment[0];
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break;
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default:
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BUG();
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break;
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}
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return base + internal_offset;
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return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
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(adev->reg_offset[SDMA1_HWIP][0][0] + offset));
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}
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static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
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@ -265,8 +253,8 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
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int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
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wptr = &local_wptr;
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lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;
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highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
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lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
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highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
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DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
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me, highbit, lowbit);
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@ -315,8 +303,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
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lower_32_bits(ring->wptr << 2),
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me,
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upper_32_bits(ring->wptr << 2));
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WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
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WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
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WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
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WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
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}
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}
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@ -460,12 +448,12 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
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amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
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for (i = 0; i < adev->sdma.num_instances; i++) {
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rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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}
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sdma0->ready = false;
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@ -522,18 +510,18 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
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}
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for (i = 0; i < adev->sdma.num_instances; i++) {
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f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
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f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
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f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
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AUTO_CTXSW_ENABLE, enable ? 1 : 0);
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if (enable && amdgpu_sdma_phase_quantum) {
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE0_QUANTUM),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
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phase_quantum);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE1_QUANTUM),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
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phase_quantum);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE2_QUANTUM),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
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phase_quantum);
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}
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
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}
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}
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@ -557,9 +545,9 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
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}
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for (i = 0; i < adev->sdma.num_instances; i++) {
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f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
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f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
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f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
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}
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}
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@ -587,48 +575,48 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
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ring = &adev->sdma.instance[i].ring;
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wb_offset = (ring->rptr_offs * 4);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
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/* Set ring buffer size in dwords */
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
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#ifdef __BIG_ENDIAN
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
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RPTR_WRITEBACK_SWAP_ENABLE, 1);
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#endif
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
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/* set the wb address whether it's enabled or not */
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
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upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
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lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
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ring->wptr = 0;
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/* before programing wptr to a less value, need set minor_ptr_update first */
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
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if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
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}
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doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL));
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doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET));
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doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
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doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
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if (ring->use_doorbell) {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
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@ -637,8 +625,8 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
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} else {
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doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
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}
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
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else
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@ -648,44 +636,44 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
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sdma_v4_0_ring_set_wptr(ring);
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/* set minor_ptr_update to 0 after wptr programed */
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
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/* set utc l1 enable flag always to 1 */
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temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
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temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
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if (!amdgpu_sriov_vf(adev)) {
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/* unhalt engine */
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temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
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temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
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temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
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}
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/* setup the wptr shadow polling */
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wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
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lower_32_bits(wptr_gpu_addr));
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
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upper_32_bits(wptr_gpu_addr));
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wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
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wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
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if (amdgpu_sriov_vf(adev))
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
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else
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
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/* enable DMA RB */
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
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ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
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ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
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#ifdef __BIG_ENDIAN
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ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
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#endif
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/* enable DMA IBs */
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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ring->ready = true;
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@ -816,12 +804,12 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
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(adev->sdma.instance[i].fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
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for (j = 0; j < fw_size; j++)
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
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WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
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}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1317,7 +1305,7 @@ static bool sdma_v4_0_is_idle(void *handle)
|
|||
u32 i;
|
||||
|
||||
for (i = 0; i < adev->sdma.num_instances; i++) {
|
||||
u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));
|
||||
u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
|
||||
|
||||
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
|
||||
return false;
|
||||
|
|
@ -1333,8 +1321,8 @@ static int sdma_v4_0_wait_for_idle(void *handle)
|
|||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
for (i = 0; i < adev->usec_timeout; i++) {
|
||||
sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));
|
||||
sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
|
||||
sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
|
||||
sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
|
||||
|
||||
if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
|
||||
return 0;
|
||||
|
|
@ -1358,8 +1346,8 @@ static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
|
|||
u32 sdma_cntl;
|
||||
|
||||
u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
|
||||
sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) :
|
||||
sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL);
|
||||
sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
|
||||
sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
|
||||
|
||||
sdma_cntl = RREG32(reg_offset);
|
||||
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
|
||||
|
|
|
|||
|
|
@ -54,42 +54,24 @@ struct nbio_pcie_index_data {
|
|||
(ip##_BASE__INST##inst##_SEG4 + reg)))))
|
||||
|
||||
#define WREG32_FIELD15(ip, idx, reg, field, val) \
|
||||
WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
|
||||
WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
|
||||
(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
|
||||
& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
|
||||
|
||||
#define RREG32_SOC15(ip, inst, reg) \
|
||||
RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
|
||||
(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
|
||||
(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
|
||||
(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
|
||||
(ip##_BASE__INST##inst##_SEG4 + reg))))))
|
||||
RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
|
||||
|
||||
#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
|
||||
RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
|
||||
(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
|
||||
(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
|
||||
(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
|
||||
(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset)
|
||||
RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
|
||||
|
||||
#define WREG32_SOC15(ip, inst, reg, value) \
|
||||
WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
|
||||
(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
|
||||
(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
|
||||
(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
|
||||
(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
|
||||
WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
|
||||
|
||||
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
|
||||
WREG32_NO_KIQ( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
|
||||
(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
|
||||
(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
|
||||
(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
|
||||
(ip##_BASE__INST##inst##_SEG4 + reg))))), value)
|
||||
WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
|
||||
|
||||
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
|
||||
WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
|
||||
(1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
|
||||
(2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
|
||||
(3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
|
||||
(ip##_BASE__INST##inst##_SEG4 + reg))))) + offset, value)
|
||||
WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue