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dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM

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Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.

This patch adds clock ID for this to dt-binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1608585459-17250-2-git-send-email-skomatineni@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sowjanya Komatineni 2020-12-21 13:17:31 -08:00 committed by Mark Brown
parent 74523a5dae
commit b499779761
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GPG key ID: 24D68B725D5487D0
1 changed files with 1 additions and 1 deletions
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2
include/dt-bindings/clock/tegra210-car.h
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@ -307,7 +307,7 @@
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
/* 277 */
/* 278 */
#define TEGRA210_CLK_QSPI_PM 278
/* 279 */
/* 280 */
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */