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dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode. This patch adds clock ID for this to dt-binding. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -307,7 +307,7 @@
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#define TEGRA210_CLK_AUDIO4 275
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#define TEGRA210_CLK_SPDIF 276
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/* 277 */
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/* 278 */
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#define TEGRA210_CLK_QSPI_PM 278
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/* 279 */
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/* 280 */
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#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
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