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riscv: mm: fix regression due to update_mmu_cache change
This is a partial revert of the commit4bd1d80efb
("riscv: mm: notify remote harts about mmu cache updates"). Original commit included two loosely related changes serving the same purpose of fixing stale TLB entries causing user-space application crash: - introduce deferred per-ASID TLB flush for CPUs not running the task - switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache According to report and discussion in [1], the second part caused a regression on Renesas RZ/Five SoC. For now restore the old behavior of the update_mmu_cache. [1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/ Fixes:4bd1d80efb
("riscv: mm: notify remote harts about mmu cache updates") Reported-by: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Link: trailer, so that it can be parsed with git's trailer functionality? Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230129211818.686557-1-geomatsi@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -415,7 +415,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
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* Relying on flush_tlb_fix_spurious_fault would suffice, but
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* the extra traps reduce performance. So, eagerly SFENCE.VMA.
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*/
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flush_tlb_page(vma, address);
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local_flush_tlb_page(address);
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}
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#define __HAVE_ARCH_UPDATE_MMU_TLB
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