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arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board
Add the PCIe support on iMX8MM EVK boards. And set the default reference clock mode. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -5,6 +5,7 @@
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/dts-v1/;
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include <dt-bindings/usb/pd.h>
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#include "imx8mm.dtsi"
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@ -30,6 +31,23 @@ status {
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_pcie0: regulator-pcie {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0_reg>;
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regulator-name = "MPCIE_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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@ -296,6 +314,30 @@ pca6416: gpio@20 {
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};
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};
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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fsl,tx-deemph-gen1 = <0x2d>;
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fsl,tx-deemph-gen2 = <0xf>;
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clocks = <&pcie0_refclk>;
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status = "okay";
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
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<&pcie0_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_bus";
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assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
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<&clk IMX8MM_CLK_PCIE1_CTRL>;
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assigned-clock-rates = <10000000>, <250000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
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<&clk IMX8MM_SYS_PLL2_250M>;
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vpcie-supply = <®_pcie0>;
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status = "okay";
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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@ -413,6 +455,19 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
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MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
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>;
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};
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pinctrl_pcie0_reg: pcie0reggrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
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>;
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};
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pinctrl_pmic: pmicirqgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
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