mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 10:29:37 +00:00
powerpc/perf: Fix sampled instruction type for larx/stcx
Sampled Instruction Event Register (SIER) field [46:48] identifies the
sampled instruction type. ISA v3.1 says value of 0b111 for this field as
reserved, but in POWER10 it denotes LARX/STCX type which will hopefully
be fixed in ISA v3.1 update.
Patch fixes the functions to handle type value 7 for CPU_FTR_ARCH_31.
Fixes: a64e697cef
("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Avoid reading mmcra until necessary, use early return to deindent if block]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1614858937-1485-1-git-send-email-atrajeev@linux.vnet.ibm.com
This commit is contained in:
parent
0bd3f9e953
commit
b4ded42268
2 changed files with 34 additions and 5 deletions
|
@ -275,11 +275,39 @@ void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
|
|||
|
||||
sier = mfspr(SPRN_SIER);
|
||||
val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
|
||||
if (val == 1 || val == 2) {
|
||||
idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
|
||||
sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
|
||||
if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31)))
|
||||
return;
|
||||
|
||||
dsrc->val = isa207_find_source(idx, sub_idx);
|
||||
idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
|
||||
sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
|
||||
|
||||
dsrc->val = isa207_find_source(idx, sub_idx);
|
||||
if (val == 7) {
|
||||
u64 mmcra;
|
||||
u32 op_type;
|
||||
|
||||
/*
|
||||
* Type 0b111 denotes either larx or stcx instruction. Use the
|
||||
* MMCRA sampling bits [57:59] along with the type value
|
||||
* to determine the exact instruction type. If the sampling
|
||||
* criteria is neither load or store, set the type as default
|
||||
* to NA.
|
||||
*/
|
||||
mmcra = mfspr(SPRN_MMCRA);
|
||||
|
||||
op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK;
|
||||
switch (op_type) {
|
||||
case 5:
|
||||
dsrc->val |= P(OP, LOAD);
|
||||
break;
|
||||
case 7:
|
||||
dsrc->val |= P(OP, STORE);
|
||||
break;
|
||||
default:
|
||||
dsrc->val |= P(OP, NA);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
|
||||
}
|
||||
}
|
||||
|
@ -297,7 +325,7 @@ void isa207_get_mem_weight(u64 *weight, u64 type)
|
|||
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
||||
mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
|
||||
|
||||
if (val == 0 || val == 7)
|
||||
if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31)))
|
||||
weight_lat = 0;
|
||||
else
|
||||
weight_lat = mantissa << (2 * exp);
|
||||
|
|
|
@ -220,6 +220,7 @@
|
|||
/* Bits in MMCRA for PowerISA v2.07 */
|
||||
#define MMCRA_SAMP_MODE_SHIFT 1
|
||||
#define MMCRA_SAMP_ELIG_SHIFT 4
|
||||
#define MMCRA_SAMP_ELIG_MASK 7
|
||||
#define MMCRA_THR_CTL_SHIFT 8
|
||||
#define MMCRA_THR_SEL_SHIFT 16
|
||||
#define MMCRA_THR_CMP_SHIFT 32
|
||||
|
|
Loading…
Reference in a new issue