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qed: Add qed APIs for PHY module query.
This patch adds qed APIs for reading the PHY module. Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com> Signed-off-by: Ariel Elior <ariel.elior@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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5 changed files with 119 additions and 0 deletions
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@ -12444,6 +12444,8 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
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#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
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#define DRV_MSG_CODE_STATS_TYPE_RDMA 4
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#define DRV_MSG_CODE_STATS_TYPE_RDMA 4
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#define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
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#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
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#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
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#define DRV_MSG_CODE_BIST_TEST 0x001e0000
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#define DRV_MSG_CODE_BIST_TEST 0x001e0000
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@ -12543,6 +12545,15 @@ struct public_drv_mb {
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#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
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#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
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#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
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#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
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#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
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#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
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#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
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#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
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#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
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#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
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#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
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#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
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/* Resource Allocation params - Driver version support */
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/* Resource Allocation params - Driver version support */
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#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
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#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
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#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
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#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
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@ -12596,6 +12607,9 @@ struct public_drv_mb {
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#define FW_MSG_CODE_PHY_OK 0x00110000
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#define FW_MSG_CODE_PHY_OK 0x00110000
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#define FW_MSG_CODE_OK 0x00160000
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#define FW_MSG_CODE_OK 0x00160000
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#define FW_MSG_CODE_ERROR 0x00170000
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#define FW_MSG_CODE_ERROR 0x00170000
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#define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
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#define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
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#define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
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#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
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#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
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#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
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#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
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@ -12687,6 +12701,8 @@ struct mcp_public_data {
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struct public_func func[MCP_GLOB_FUNC_MAX];
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struct public_func func[MCP_GLOB_FUNC_MAX];
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};
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};
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#define MAX_I2C_TRANSACTION_SIZE 16
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/* OCBB definitions */
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/* OCBB definitions */
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enum tlvs {
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enum tlvs {
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/* Category 1: Device Properties */
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/* Category 1: Device Properties */
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@ -2102,6 +2102,28 @@ static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
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return status;
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return status;
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}
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}
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static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
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u8 dev_addr, u32 offset, u32 len)
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{
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struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *ptt;
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int rc = 0;
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if (IS_VF(cdev))
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return 0;
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ptt = qed_ptt_acquire(hwfn);
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if (!ptt)
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return -EAGAIN;
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rc = qed_mcp_phy_sfp_read(hwfn, ptt, MFW_PORT(hwfn), dev_addr,
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offset, len, buf);
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qed_ptt_release(hwfn, ptt);
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return rc;
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}
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static struct qed_selftest_ops qed_selftest_ops_pass = {
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static struct qed_selftest_ops qed_selftest_ops_pass = {
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.selftest_memory = &qed_selftest_memory,
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.selftest_memory = &qed_selftest_memory,
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.selftest_interrupt = &qed_selftest_interrupt,
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.selftest_interrupt = &qed_selftest_interrupt,
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@ -2144,6 +2166,7 @@ const struct qed_common_ops qed_common_ops_pass = {
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.update_mac = &qed_update_mac,
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.update_mac = &qed_update_mac,
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.update_mtu = &qed_update_mtu,
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.update_mtu = &qed_update_mtu,
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.update_wol = &qed_update_wol,
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.update_wol = &qed_update_wol,
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.read_module_eeprom = &qed_read_module_eeprom,
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};
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};
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void qed_get_protocol_stats(struct qed_dev *cdev,
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void qed_get_protocol_stats(struct qed_dev *cdev,
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@ -2463,6 +2463,55 @@ int qed_mcp_nvm_write(struct qed_dev *cdev,
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return rc;
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return rc;
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}
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}
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int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf)
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{
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u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0;
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u32 resp, param;
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int rc;
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nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) &
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DRV_MB_PARAM_TRANSCEIVER_PORT_MASK;
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nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) &
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DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK;
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addr = offset;
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offset = 0;
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bytes_left = len;
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while (bytes_left > 0) {
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bytes_to_copy = min_t(u32, bytes_left,
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MAX_I2C_TRANSACTION_SIZE);
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nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
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DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
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nvm_offset |= ((addr + offset) <<
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DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) &
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DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK;
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nvm_offset |= (bytes_to_copy <<
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DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) &
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DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK;
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rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
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DRV_MSG_CODE_TRANSCEIVER_READ,
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nvm_offset, &resp, ¶m, &buf_size,
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(u32 *)(p_buf + offset));
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if (rc) {
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DP_NOTICE(p_hwfn,
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"Failed to send a transceiver read command to the MFW. rc = %d.\n",
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rc);
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return rc;
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}
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if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
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return -ENODEV;
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else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
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return -EINVAL;
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offset += buf_size;
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bytes_left -= buf_size;
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}
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return 0;
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}
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int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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{
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u32 drv_mb_param = 0, rsp, param;
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u32 drv_mb_param = 0, rsp, param;
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@ -839,6 +839,22 @@ int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
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u32 *o_mcp_resp,
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u32 *o_mcp_resp,
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u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf);
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u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf);
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/**
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* @brief Read from sfp
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*
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* @param p_hwfn - hw function
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* @param p_ptt - PTT required for register access
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* @param port - transceiver port
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* @param addr - I2C address
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* @param offset - offset in sfp
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* @param len - buffer length
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* @param p_buf - buffer to read into
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*
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* @return int - 0 - operation was successful.
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*/
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int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
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u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf);
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/**
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/**
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* @brief indicates whether the MFW objects [under mcp_info] are accessible
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* @brief indicates whether the MFW objects [under mcp_info] are accessible
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*
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*
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@ -759,6 +759,9 @@ struct qed_generic_tlvs {
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u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
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u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
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};
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};
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#define QED_I2C_DEV_ADDR_A0 0xA0
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#define QED_I2C_DEV_ADDR_A2 0xA2
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#define QED_NVM_SIGNATURE 0x12435687
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#define QED_NVM_SIGNATURE 0x12435687
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enum qed_nvm_flash_cmd {
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enum qed_nvm_flash_cmd {
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@ -1026,6 +1029,18 @@ struct qed_common_ops {
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* @param enabled - true iff WoL should be enabled.
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* @param enabled - true iff WoL should be enabled.
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*/
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*/
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int (*update_wol) (struct qed_dev *cdev, bool enabled);
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int (*update_wol) (struct qed_dev *cdev, bool enabled);
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/**
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* @brief read_module_eeprom
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*
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* @param cdev
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* @param buf - buffer
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* @param dev_addr - PHY device memory region
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* @param offset - offset into eeprom contents to be read
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* @param len - buffer length, i.e., max bytes to be read
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*/
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int (*read_module_eeprom)(struct qed_dev *cdev,
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char *buf, u8 dev_addr, u32 offset, u32 len);
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};
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};
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#define MASK_FIELD(_name, _value) \
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#define MASK_FIELD(_name, _value) \
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