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pinctrl: rockchip: add drive-strength control for rk3288
The rk3288 is the first Rockchip soc handling the drive strength on a per-pin basis, while the older ones can set the drive-strength only for specific pin-groups. Therefore limit setting the drive-strength to this soc for now. Signed-off-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1 changed files with 112 additions and 0 deletions
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@ -573,6 +573,98 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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}
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}
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#define RK3288_DRV_PMU_OFFSET 0x70
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#define RK3288_DRV_GRF_OFFSET 0x1c0
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#define RK3288_DRV_BITS_PER_PIN 2
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#define RK3288_DRV_PINS_PER_REG 8
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#define RK3288_DRV_BANK_STRIDE 16
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static int rk3288_drv_list[] = { 2, 4, 8, 12 };
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static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = RK3288_DRV_PMU_OFFSET;
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*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK3288_DRV_PINS_PER_REG;
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*bit *= RK3288_DRV_BITS_PER_PIN;
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} else {
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*regmap = info->regmap_base;
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*reg = RK3288_DRV_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
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*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
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*bit *= RK3288_DRV_BITS_PER_PIN;
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}
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}
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static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = regmap_read(regmap, reg, &data);
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if (ret)
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return ret;
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data >>= bit;
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data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
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return rk3288_drv_list[data];
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}
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static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
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int strength)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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struct regmap *regmap;
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unsigned long flags;
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int reg, ret, i;
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u32 data;
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u8 bit;
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rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
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if (rk3288_drv_list[i] == strength) {
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ret = i;
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break;
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}
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}
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if (ret < 0) {
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dev_err(info->dev, "unsupported driver strength %d\n",
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strength);
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return ret;
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}
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spin_lock_irqsave(&bank->slock, flags);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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spin_unlock_irqrestore(&bank->slock, flags);
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return ret;
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}
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static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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@ -870,6 +962,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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if (rc)
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return rc;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* rk3288 is the first with per-pin drive-strength */
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if (info->ctrl->type != RK3288)
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return -ENOTSUPP;
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rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
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if (rc < 0)
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return rc;
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break;
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default:
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return -ENOTSUPP;
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break;
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@ -919,6 +1020,17 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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arg = rc ? 1 : 0;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* rk3288 is the first with per-pin drive-strength */
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if (info->ctrl->type != RK3288)
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return -ENOTSUPP;
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rc = rk3288_get_drive(bank, pin - bank->pin_base);
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if (rc < 0)
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return rc;
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arg = rc;
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break;
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default:
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return -ENOTSUPP;
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break;
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