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clk: qcom: Add some missing gcc clks for msm8996
Add a few missing gcc clks for msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: omit aggre0_noc_qosgen_extref_clk] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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5b394b2ddf
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2 changed files with 161 additions and 0 deletions
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@ -260,6 +260,36 @@ static struct clk_alpha_pll_postdiv gpll0 = {
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},
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};
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static struct clk_branch gcc_mmss_gpll0_div_clk = {
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x5200c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mmss_gpll0_div_clk",
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.parent_names = (const char *[]){ "gpll0" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_mss_gpll0_div_clk = {
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x5200c,
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.enable_mask = BIT(2),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mss_gpll0_div_clk",
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.parent_names = (const char *[]){ "gpll0" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops
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},
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},
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};
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static struct clk_alpha_pll gpll4_early = {
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.offset = 0x77000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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@ -2951,6 +2981,20 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
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},
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};
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static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
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.halt_reg = 0x82014,
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.clkr = {
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.enable_reg = 0x82014,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre1_pnoc_ahb_clk",
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.parent_names = (const char *[]){ "periph_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_aggre2_ufs_axi_clk = {
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.halt_reg = 0x83014,
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.clkr = {
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@ -2981,6 +3025,34 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
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},
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};
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static struct clk_branch gcc_dcc_ahb_clk = {
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.halt_reg = 0x84004,
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.clkr = {
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.enable_reg = 0x84004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_dcc_ahb_clk",
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.parent_names = (const char *[]){ "config_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
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.halt_reg = 0x85000,
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.clkr = {
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.enable_reg = 0x85000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
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.parent_names = (const char *[]){ "config_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_qspi_ahb_clk = {
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.halt_reg = 0x8b004,
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.clkr = {
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@ -3039,6 +3111,20 @@ static struct clk_branch gcc_hdmi_clkref_clk = {
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},
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};
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static struct clk_branch gcc_edp_clkref_clk = {
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.halt_reg = 0x88004,
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.clkr = {
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.enable_reg = 0x88004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_edp_clkref_clk",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_ufs_clkref_clk = {
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.halt_reg = 0x88008,
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.clkr = {
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@ -3095,6 +3181,62 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
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},
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};
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static struct clk_branch gcc_mss_cfg_ahb_clk = {
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.halt_reg = 0x8a000,
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.clkr = {
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.enable_reg = 0x8a000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mss_cfg_ahb_clk",
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.parent_names = (const char *[]){ "config_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
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.halt_reg = 0x8a004,
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.clkr = {
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.enable_reg = 0x8a004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mss_mnoc_bimc_axi_clk",
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.parent_names = (const char *[]){ "system_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_mss_snoc_axi_clk = {
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.halt_reg = 0x8a024,
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.clkr = {
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.enable_reg = 0x8a024,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mss_snoc_axi_clk",
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.parent_names = (const char *[]){ "system_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
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.halt_reg = 0x8a028,
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.clkr = {
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.enable_reg = 0x8a028,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_mss_q6_bimc_axi_clk",
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.parent_names = (const char *[]){ "system_noc_clk_src" },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_hw *gcc_msm8996_hws[] = {
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&xo.hw,
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&gpll0_early_div.hw,
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@ -3355,6 +3497,7 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
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[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
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[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
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[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
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[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
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[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
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[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
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[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
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@ -3365,6 +3508,15 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
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[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
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[GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
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[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
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[GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
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[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
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[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
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[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
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[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
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[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
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[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
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[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
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[GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
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};
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static struct gdsc *gcc_msm8996_gdscs[] = {
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@ -235,6 +235,15 @@
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#define GCC_RX1_USB2_CLKREF_CLK 218
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#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
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#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
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#define GCC_EDP_CLKREF_CLK 221
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#define GCC_MSS_CFG_AHB_CLK 222
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#define GCC_MSS_Q6_BIMC_AXI_CLK 223
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#define GCC_MSS_SNOC_AXI_CLK 224
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#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
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#define GCC_DCC_AHB_CLK 226
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#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
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#define GCC_MMSS_GPLL0_DIV_CLK 228
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#define GCC_MSS_GPLL0_DIV_CLK 229
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#define GCC_SYSTEM_NOC_BCR 0
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#define GCC_CONFIG_NOC_BCR 1
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