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ARM: EXYNOS: SWRESET is needed to boot secondary CPU on exynos3250
Without software reset the secondary CPU does not power up and exynos_boot_secondary() ends with pen_release equal to 1. This can be observed in dmesg: CPU1: failed to come online Brought up 1 CPUs SMP: Total of 1 processors activated. CPU: All CPU(s) started in SVC mode. When booting the secondary CPU on Exynos3250 execute also software reset for core 1. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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2 changed files with 25 additions and 0 deletions
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@ -120,6 +120,26 @@ static inline void __iomem *cpu_boot_reg(int cpu)
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return boot_reg;
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}
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/*
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* Set wake up by local power mode and execute software reset for given core.
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*
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* Currently this is needed only when booting secondary CPU on Exynos3250.
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*/
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static void exynos_core_restart(u32 core_id)
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{
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u32 val;
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if (!of_machine_is_compatible("samsung,exynos3250"))
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return;
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val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
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val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
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pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
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pr_info("CPU%u: Software reset\n", core_id);
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pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
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}
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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@ -196,6 +216,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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return -ETIMEDOUT;
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}
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}
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exynos_core_restart(core_id);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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@ -21,6 +21,7 @@
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#define S5P_USE_STANDBY_WFI0 (1 << 16)
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#define S5P_USE_STANDBY_WFE0 (1 << 24)
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#define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n)
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#define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28)
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#define EXYNOS_SWRESET 0x0400
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#define EXYNOS5440_SWRESET 0x00C4
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@ -125,6 +126,7 @@
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#define S5P_PAD_RET_EBIB_OPTION 0x31A8
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#define S5P_CORE_LOCAL_PWR_EN 0x3
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#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8)
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/* Only for EXYNOS4210 */
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#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
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