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irqchip: GICv3: Add support for irq_[get, set]_irqchip_state()
Add the required hooks for the internal state of an interrupt to be exposed to other subsystems. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Phong Vo <pvo@apm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tin Huynh <tnhuynh@apm.com> Cc: Y Vo <yvo@apm.com> Cc: Toan Le <toanle@apm.com> Cc: Bjorn Andersson <bjorn@kryo.se> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Arnd Bergmann <arnd@arndb.de> Link: http://lkml.kernel.org/r/1426676484-21812-4-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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parent
567178077c
commit
b594c6e20c
1 changed files with 70 additions and 13 deletions
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@ -195,6 +195,19 @@ static void gic_enable_redist(bool enable)
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/*
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* Routines to disable, enable, EOI and route interrupts
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*/
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void __iomem *base;
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
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}
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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@ -223,6 +236,61 @@ static void gic_unmask_irq(struct irq_data *d)
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gic_poke_irq(d, GICD_ISENABLER);
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}
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static int gic_irq_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool val)
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{
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u32 reg;
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if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
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return -EINVAL;
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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reg = val ? GICD_ISPENDR : GICD_ICPENDR;
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break;
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case IRQCHIP_STATE_ACTIVE:
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reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
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break;
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case IRQCHIP_STATE_MASKED:
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reg = val ? GICD_ICENABLER : GICD_ISENABLER;
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break;
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default:
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return -EINVAL;
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}
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gic_poke_irq(d, reg);
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return 0;
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}
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static int gic_irq_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool *val)
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{
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if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
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return -EINVAL;
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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*val = gic_peek_irq(d, GICD_ISPENDR);
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break;
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case IRQCHIP_STATE_ACTIVE:
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*val = gic_peek_irq(d, GICD_ISACTIVER);
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break;
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case IRQCHIP_STATE_MASKED:
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*val = !gic_peek_irq(d, GICD_ISENABLER);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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gic_write_eoir(gic_irq(d));
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@ -418,19 +486,6 @@ static void gic_cpu_init(void)
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}
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#ifdef CONFIG_SMP
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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void __iomem *base;
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if (gic_irq_in_rdist(d))
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base = gic_data_rdist_sgi_base();
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else
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base = gic_data.dist_base;
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return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
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}
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static int gic_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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@ -601,6 +656,8 @@ static struct irq_chip gic_chip = {
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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.irq_set_affinity = gic_set_affinity,
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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};
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#define GIC_ID_NR (1U << gic_data.rdists.id_bits)
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