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drm/armada: push interlace calculation into armada_drm_plane_calc()
Push the interlaced frame calculation down into armada_drm_plane_calc() which needs to apply the same correction for both the overlay and primary planes. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
parent
4aafe00e2f
commit
b5bae71a79
3 changed files with 30 additions and 28 deletions
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@ -131,21 +131,21 @@ static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
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old_state->fb != state->fb) {
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const struct drm_format_info *format;
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u16 src_x, pitches[3];
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u32 addrs[3];
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u32 addrs[2][3];
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armada_drm_plane_calc(state, addrs, pitches);
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armada_drm_plane_calc(state, addrs, pitches, false);
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armada_reg_queue_set(regs, idx, addrs[0],
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armada_reg_queue_set(regs, idx, addrs[0][0],
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LCD_SPU_DMA_START_ADDR_Y0);
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armada_reg_queue_set(regs, idx, addrs[1],
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armada_reg_queue_set(regs, idx, addrs[0][1],
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LCD_SPU_DMA_START_ADDR_U0);
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armada_reg_queue_set(regs, idx, addrs[2],
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armada_reg_queue_set(regs, idx, addrs[0][2],
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LCD_SPU_DMA_START_ADDR_V0);
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armada_reg_queue_set(regs, idx, addrs[0],
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armada_reg_queue_set(regs, idx, addrs[1][0],
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LCD_SPU_DMA_START_ADDR_Y1);
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armada_reg_queue_set(regs, idx, addrs[1],
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armada_reg_queue_set(regs, idx, addrs[1][1],
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LCD_SPU_DMA_START_ADDR_U1);
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armada_reg_queue_set(regs, idx, addrs[2],
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armada_reg_queue_set(regs, idx, addrs[1][2],
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LCD_SPU_DMA_START_ADDR_V1);
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val = pitches[0] << 16 | pitches[0];
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@ -35,8 +35,8 @@ static const uint32_t armada_primary_formats[] = {
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DRM_FORMAT_BGR565,
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};
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void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3],
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u16 pitches[3])
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void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3],
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u16 pitches[3], bool interlaced)
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{
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struct drm_framebuffer *fb = state->fb;
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const struct drm_format_info *format = fb->format;
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@ -52,43 +52,45 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3],
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if (num_planes > 3)
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num_planes = 3;
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addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
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x * format->cpp[0];
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addrs[0][0] = addr + fb->offsets[0] + y * fb->pitches[0] +
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x * format->cpp[0];
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pitches[0] = fb->pitches[0];
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y /= format->vsub;
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x /= format->hsub;
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for (i = 1; i < num_planes; i++) {
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addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
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x * format->cpp[i];
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addrs[0][i] = addr + fb->offsets[i] + y * fb->pitches[i] +
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x * format->cpp[i];
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pitches[i] = fb->pitches[i];
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}
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for (; i < 3; i++) {
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addrs[i] = 0;
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addrs[0][i] = 0;
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pitches[i] = 0;
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}
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if (interlaced) {
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for (i = 0; i < 3; i++) {
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addrs[1][i] = addrs[0][i] + pitches[i];
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pitches[i] *= 2;
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}
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} else {
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for (i = 0; i < 3; i++)
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addrs[1][i] = addrs[0][i];
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}
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}
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static unsigned armada_drm_crtc_calc_fb(struct drm_plane_state *state,
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struct armada_regs *regs, bool interlaced)
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{
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u16 pitches[3];
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u32 addrs[3], addr_odd, addr_even;
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u32 addrs[2][3];
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unsigned i = 0;
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armada_drm_plane_calc(state, addrs, pitches);
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addr_odd = addr_even = addrs[0];
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if (interlaced) {
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addr_even += pitches[0];
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pitches[0] *= 2;
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}
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armada_drm_plane_calc(state, addrs, pitches, interlaced);
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/* write offset, base, and pitch */
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armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
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armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
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armada_reg_queue_set(regs, i, addrs[0][0], LCD_CFG_GRA_START_ADDR0);
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armada_reg_queue_set(regs, i, addrs[1][0], LCD_CFG_GRA_START_ADDR1);
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armada_reg_queue_mod(regs, i, pitches[0], 0xffff, LCD_CFG_GRA_PITCH);
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return i;
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@ -1,8 +1,8 @@
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#ifndef ARMADA_PLANE_H
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#define ARMADA_PLANE_H
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void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[3],
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u16 pitches[3]);
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void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3],
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u16 pitches[3], bool interlaced);
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int armada_drm_plane_prepare_fb(struct drm_plane *plane,
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struct drm_plane_state *state);
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void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
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