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irqchip/gic-v3: Factor group0 detection into functions
The code to detect whether Linux has access to group0 interrupts can prove useful in other parts of the driver. Provide a separate function to do this. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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1 changed files with 36 additions and 19 deletions
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@ -400,6 +400,39 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
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}
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}
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static u32 gic_get_pribits(void)
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{
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u32 pribits;
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pribits = gic_read_ctlr();
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pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
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pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
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pribits++;
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return pribits;
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}
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static bool gic_has_group0(void)
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{
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u32 val;
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/*
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* Let's find out if Group0 is under control of EL3 or not by
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* setting the highest possible, non-zero priority in PMR.
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*
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* If SCR_EL3.FIQ is set, the priority gets shifted down in
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* order for the CPU interface to set bit 7, and keep the
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* actual priority in the non-secure range. In the process, it
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* looses the least significant bit and the actual priority
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* becomes 0x80. Reading it back returns 0, indicating that
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* we're don't have access to Group0.
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*/
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gic_write_pmr(BIT(8 - gic_get_pribits()));
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val = gic_read_pmr();
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return val != 0;
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}
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static void __init gic_dist_init(void)
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{
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unsigned int i;
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@ -541,7 +574,7 @@ static void gic_cpu_sys_reg_init(void)
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u64 mpidr = cpu_logical_map(cpu);
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u64 need_rss = MPIDR_RS(mpidr);
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bool group0;
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u32 val, pribits;
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u32 pribits;
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/*
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* Need to check that the SRE bit has actually been set. If
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@ -553,25 +586,9 @@ static void gic_cpu_sys_reg_init(void)
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if (!gic_enable_sre())
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pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
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pribits = gic_read_ctlr();
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pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
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pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
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pribits++;
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pribits = gic_get_pribits();
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/*
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* Let's find out if Group0 is under control of EL3 or not by
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* setting the highest possible, non-zero priority in PMR.
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*
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* If SCR_EL3.FIQ is set, the priority gets shifted down in
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* order for the CPU interface to set bit 7, and keep the
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* actual priority in the non-secure range. In the process, it
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* looses the least significant bit and the actual priority
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* becomes 0x80. Reading it back returns 0, indicating that
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* we're don't have access to Group0.
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*/
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write_gicreg(BIT(8 - pribits), ICC_PMR_EL1);
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val = read_gicreg(ICC_PMR_EL1);
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group0 = val != 0;
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group0 = gic_has_group0();
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/* Set priority mask register */
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write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
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