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MIPS: Add Cavium OCTEON cop2/cvmseg state entries to processor.h.
Add in the cop2 and cvmseg state info to the known proc reg data for Cavium so that it can be tracked, saved, restored. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 69 additions and 0 deletions
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@ -118,6 +118,60 @@ union mips_watch_reg_state {
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struct mips3264_watch_reg_state mips3264;
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};
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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struct octeon_cop2_state {
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/* DMFC2 rt, 0x0201 */
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unsigned long cop2_crc_iv;
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/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
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unsigned long cop2_crc_length;
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/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
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unsigned long cop2_crc_poly;
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/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
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unsigned long cop2_llm_dat[2];
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/* DMFC2 rt, 0x0084 */
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unsigned long cop2_3des_iv;
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/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
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unsigned long cop2_3des_key[3];
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/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
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unsigned long cop2_3des_result;
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/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
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unsigned long cop2_aes_inp0;
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/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
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unsigned long cop2_aes_iv[2];
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/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
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* rt, 0x0107 */
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unsigned long cop2_aes_key[4];
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/* DMFC2 rt, 0x0110 */
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unsigned long cop2_aes_keylen;
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/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
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unsigned long cop2_aes_result[2];
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/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
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* rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
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* 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
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* 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
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* 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
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unsigned long cop2_hsh_datw[15];
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/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
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* rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
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* 0x0256; DMFC2 rt, 0x0257 - Pass2 */
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unsigned long cop2_hsh_ivw[8];
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/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
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unsigned long cop2_gfm_mult[2];
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/* DMFC2 rt, 0x025E - Pass2 */
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unsigned long cop2_gfm_poly;
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/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
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unsigned long cop2_gfm_result[2];
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};
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#define INIT_OCTEON_COP2 {0,}
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struct octeon_cvmseg_state {
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unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
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[cpu_dcache_line_size() / sizeof(unsigned long)];
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};
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#endif
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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@ -160,6 +214,10 @@ struct thread_struct {
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unsigned long trap_no;
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unsigned long irix_trampoline; /* Wheee... */
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unsigned long irix_oldctx;
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
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struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
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#endif
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struct mips_abi *abi;
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};
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@ -171,6 +229,13 @@ struct thread_struct {
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#define FPAFF_INIT
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#endif /* CONFIG_MIPS_MT_FPAFF */
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define OCTEON_INIT \
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.cp2 = INIT_OCTEON_COP2,
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#else
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#define OCTEON_INIT
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#define INIT_THREAD { \
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/* \
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* Saved main processor registers \
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@ -221,6 +286,10 @@ struct thread_struct {
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.trap_no = 0, \
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.irix_trampoline = 0, \
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.irix_oldctx = 0, \
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/* \
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* Cavium Octeon specifics (null if not Octeon) \
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*/ \
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OCTEON_INIT \
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}
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struct task_struct;
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