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clk: renesas: r8a779g0: Add Z0 clock support

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Add support for the Z0 (Cortex-A76 Sub-System) clock on R-Car V4H, based
on the existing support for Z clocks on R-Car Gen4.

Extracted from a patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/75daa1fd8fa7eaef7b8945bb5906c787222c7ac4.1668423063.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-11-14 11:51:58 +01:00
parent 523ed9442b
commit b5f7c6a507
1 changed files with 1 additions and 0 deletions
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drivers/clk/renesas/r8a779g0-cpg-mssr.c
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@ -96,6 +96,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
/* Core Clock Outputs */
DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),