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pxamci: enable DMA for write ops after CMD/RESP
With the PXA270 MMC hardware, there seems to be an issue of data corruption on writes where a 4KB data block is offset by one byte. If we delay enabling the DMA for writes until after the CMD/RESP has finished, the problem seems to be fixed. related to PXA270 Erratum #91 Tested-by: Vernon Sauder <VernonInHand@gmail.com> Signed-off-by: Cliff Brake <cbrake@bec-systems.com> Acked-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
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e10a854c46
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b6018958a5
1 changed files with 15 additions and 1 deletions
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@ -180,7 +180,15 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
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else
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else
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DALGN &= ~(1 << host->dma);
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DALGN &= ~(1 << host->dma);
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DDADR(host->dma) = host->sg_dma;
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DDADR(host->dma) = host->sg_dma;
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DCSR(host->dma) = DCSR_RUN;
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/*
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* workaround for erratum #91:
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* only start DMA now if we are doing a read,
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* otherwise we wait until CMD/RESP has finished
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* before starting DMA.
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*/
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if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
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DCSR(host->dma) = DCSR_RUN;
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}
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}
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static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
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static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
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@ -267,6 +275,12 @@ static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
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pxamci_disable_irq(host, END_CMD_RES);
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pxamci_disable_irq(host, END_CMD_RES);
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if (host->data && !cmd->error) {
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if (host->data && !cmd->error) {
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pxamci_enable_irq(host, DATA_TRAN_DONE);
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pxamci_enable_irq(host, DATA_TRAN_DONE);
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/*
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* workaround for erratum #91, if doing write
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* enable DMA late
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*/
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if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
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DCSR(host->dma) = DCSR_RUN;
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} else {
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} else {
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pxamci_finish_request(host, host->mrq);
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pxamci_finish_request(host, host->mrq);
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}
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}
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