drm/amdgpu: add VCN_5_0_0 IP block support
Add VCN_5_0_0 IP init, ring functions, DPG support. v2: squash in warning fixes (Alex) v3: squash in block and ring init, boot, doorbell enablement, DPG support (Alex) Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -209,6 +209,7 @@ amdgpu-y += \
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vcn_v4_0.o \
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vcn_v4_0_3.o \
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vcn_v4_0_5.o \
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vcn_v5_0_0.o \
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amdgpu_jpeg.o \
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jpeg_v1_0.o \
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jpeg_v2_0.o \
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@ -160,6 +160,48 @@
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} \
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} while (0)
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#define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \
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({ \
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uint32_t internal_reg_offset, addr; \
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bool video_range, aon_range; \
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\
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addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
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addr <<= 2; \
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video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS)) && \
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((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS + 0x2600))))); \
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aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS)) && \
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((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS + 0x600))))); \
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if (video_range) \
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internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS) + \
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(VCN_VID_IP_ADDRESS)); \
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else if (aon_range) \
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internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS) + \
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(VCN_AON_IP_ADDRESS)); \
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else \
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internal_reg_offset = (0xFFFFF & addr); \
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\
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internal_reg_offset >>= 2; \
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})
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#define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \
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do { \
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if (!indirect) { \
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WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
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regUVD_DPG_LMA_DATA, value); \
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WREG32_SOC15( \
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VCN, GET_INST(VCN, inst_idx), \
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regUVD_DPG_LMA_CTL, \
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(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
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mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
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offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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} else { \
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*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
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offset; \
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*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
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value; \
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} \
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} while (0)
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#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)
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#define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4)
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#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB (1 << 6)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,37 @@
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __VCN_V5_0_0_H__
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#define __VCN_V5_0_0_H__
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#define VCN_VID_SOC_ADDRESS 0x1FC00
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#define VCN_AON_SOC_ADDRESS 0x1F800
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#define VCN1_VID_SOC_ADDRESS 0x48300
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#define VCN1_AON_SOC_ADDRESS 0x48000
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#define VCN_VID_IP_ADDRESS 0x0
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#define VCN_AON_IP_ADDRESS 0x30000
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extern const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block;
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#endif /* __VCN_V5_0_0_H__ */
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