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ARM: S5P6442: Add clock support for S5P6442
This patch adds clock support for S5P6442. This patch adds the clock register definitions and the various system clocks in S5P6442. Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com> Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Kukjin Kim
Ben Dooks
parent
5f7f6a4a0d
commit
b6f837575e
5 changed files with 595 additions and 1 deletions
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@ -12,7 +12,7 @@ obj- :=
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# Core support for S5P6442 system
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obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o
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obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o
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# machine support
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396
arch/arm/mach-s5p6442/clock.c
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396
arch/arm/mach-s5p6442/clock.c
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@ -0,0 +1,396 @@
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/* linux/arch/arm/mach-s5p6442/clock.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P6442 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/cpu-freq.h>
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#include <mach/regs-clock.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/s5p6442.h>
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
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};
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/* Possible clock sources for ARM Mux */
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static struct clk *clk_src_arm_list[] = {
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[1] = &clk_mout_apll.clk,
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[2] = &clk_mout_mpll.clk,
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};
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static struct clksrc_sources clk_src_arm = {
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.sources = clk_src_arm_list,
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.nr_sources = ARRAY_SIZE(clk_src_arm_list),
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};
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static struct clksrc_clk clk_mout_arm = {
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.clk = {
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.name = "mout_arm",
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.id = -1,
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},
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.sources = &clk_src_arm,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
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};
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static struct clk clk_dout_a2m = {
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.name = "dout_a2m",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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};
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/* Possible clock sources for D0 Mux */
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static struct clk *clk_src_d0_list[] = {
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[1] = &clk_mout_mpll.clk,
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[2] = &clk_dout_a2m,
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};
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static struct clksrc_sources clk_src_d0 = {
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.sources = clk_src_d0_list,
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.nr_sources = ARRAY_SIZE(clk_src_d0_list),
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};
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static struct clksrc_clk clk_mout_d0 = {
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.clk = {
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.name = "mout_d0",
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.id = -1,
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},
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.sources = &clk_src_d0,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
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};
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static struct clk clk_dout_apll = {
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.name = "dout_apll",
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.id = -1,
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.parent = &clk_mout_arm.clk,
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};
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/* Possible clock sources for D0SYNC Mux */
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static struct clk *clk_src_d0sync_list[] = {
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[1] = &clk_mout_d0.clk,
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[2] = &clk_dout_apll,
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};
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static struct clksrc_sources clk_src_d0sync = {
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.sources = clk_src_d0sync_list,
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.nr_sources = ARRAY_SIZE(clk_src_d0sync_list),
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};
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static struct clksrc_clk clk_mout_d0sync = {
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.clk = {
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.name = "mout_d0sync",
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.id = -1,
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},
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.sources = &clk_src_d0sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
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};
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/* Possible clock sources for D1 Mux */
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static struct clk *clk_src_d1_list[] = {
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[1] = &clk_mout_mpll.clk,
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[2] = &clk_dout_a2m,
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};
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static struct clksrc_sources clk_src_d1 = {
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.sources = clk_src_d1_list,
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.nr_sources = ARRAY_SIZE(clk_src_d1_list),
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};
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static struct clksrc_clk clk_mout_d1 = {
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.clk = {
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.name = "mout_d1",
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.id = -1,
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},
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.sources = &clk_src_d1,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
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};
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/* Possible clock sources for D1SYNC Mux */
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static struct clk *clk_src_d1sync_list[] = {
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[1] = &clk_mout_d1.clk,
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[2] = &clk_dout_apll,
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};
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static struct clksrc_sources clk_src_d1sync = {
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.sources = clk_src_d1sync_list,
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.nr_sources = ARRAY_SIZE(clk_src_d1sync_list),
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};
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static struct clksrc_clk clk_mout_d1sync = {
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.clk = {
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.name = "mout_d1sync",
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.id = -1,
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},
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.sources = &clk_src_d1sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
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};
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static struct clk clk_hclkd0 = {
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.name = "hclkd0",
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.id = -1,
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.parent = &clk_mout_d0sync.clk,
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};
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static struct clk clk_hclkd1 = {
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.name = "hclkd1",
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.id = -1,
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.parent = &clk_mout_d1sync.clk,
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};
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static struct clk clk_pclkd0 = {
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.name = "pclkd0",
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.id = -1,
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.parent = &clk_hclkd0,
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};
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static struct clk clk_pclkd1 = {
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.name = "pclkd1",
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.id = -1,
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.parent = &clk_hclkd1,
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};
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int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "dout_a2m",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
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}, {
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.clk = {
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.name = "dout_apll",
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.id = -1,
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.parent = &clk_mout_arm.clk,
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},
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.sources = &clk_src_arm,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
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}, {
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.clk = {
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.name = "hclkd1",
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.id = -1,
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.parent = &clk_mout_d1sync.clk,
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},
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.sources = &clk_src_d1sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
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}, {
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.clk = {
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.name = "hclkd0",
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.id = -1,
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.parent = &clk_mout_d0sync.clk,
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},
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.sources = &clk_src_d0sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "pclkd0",
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.id = -1,
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.parent = &clk_hclkd0,
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},
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.sources = &clk_src_d0sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
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}, {
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.clk = {
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.name = "pclkd1",
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.id = -1,
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.parent = &clk_hclkd1,
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},
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.sources = &clk_src_d1sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
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}
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};
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/* Clock initialisation code */
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static struct clksrc_clk *init_parents[] = {
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&clk_mout_apll,
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&clk_mout_mpll,
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&clk_mout_epll,
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&clk_mout_arm,
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&clk_mout_d0,
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&clk_mout_d0sync,
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&clk_mout_d1,
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&clk_mout_d1sync,
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};
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void __init_or_cpufreq s5p6442_setup_clocks(void)
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{
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struct clk *pclkd0_clk;
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struct clk *pclkd1_clk;
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unsigned long xtal;
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unsigned long arm;
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unsigned long hclkd0 = 0;
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unsigned long hclkd1 = 0;
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unsigned long pclkd0 = 0;
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unsigned long pclkd1 = 0;
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unsigned long apll;
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unsigned long mpll;
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unsigned long epll;
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unsigned int ptr;
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printk(KERN_DEBUG "%s: registering clocks\n", __func__);
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xtal = clk_get_rate(&clk_xtal);
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printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
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apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld",
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apll, mpll, epll);
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
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s3c_set_clksrc(init_parents[ptr], true);
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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arm = clk_get_rate(&clk_dout_apll);
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hclkd0 = clk_get_rate(&clk_hclkd0);
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hclkd1 = clk_get_rate(&clk_hclkd1);
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pclkd0_clk = clk_get(NULL, "pclkd0");
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BUG_ON(IS_ERR(pclkd0_clk));
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pclkd0 = clk_get_rate(pclkd0_clk);
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clk_put(pclkd0_clk);
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pclkd1_clk = clk_get(NULL, "pclkd1");
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BUG_ON(IS_ERR(pclkd1_clk));
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pclkd1 = clk_get_rate(pclkd1_clk);
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clk_put(pclkd1_clk);
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printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
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hclkd0, hclkd1, pclkd0, pclkd1);
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/* For backward compatibility */
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clk_f.rate = arm;
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clk_h.rate = hclkd1;
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clk_p.rate = pclkd1;
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clk_pclkd0.rate = pclkd0;
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clk_pclkd1.rate = pclkd1;
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}
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static struct clk init_clocks[] = {
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{
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.name = "systimer",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<17),
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<18),
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<19),
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<23),
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},
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};
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static struct clk *clks[] __initdata = {
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&clk_ext,
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&clk_epll,
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&clk_mout_apll.clk,
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&clk_mout_mpll.clk,
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&clk_mout_epll.clk,
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&clk_mout_d0.clk,
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&clk_mout_d0sync.clk,
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&clk_mout_d1.clk,
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&clk_mout_d1sync.clk,
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&clk_hclkd0,
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&clk_pclkd0,
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&clk_hclkd1,
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&clk_pclkd1,
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};
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void __init s5p6442_register_clocks(void)
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{
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s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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s3c_pwmclk_init();
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}
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69
arch/arm/mach-s5p6442/include/mach/pwm-clock.h
Normal file
69
arch/arm/mach-s5p6442/include/mach/pwm-clock.h
Normal file
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/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Copyright 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
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*
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* S5P6442 - pwm clock and timer support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_PWMCLK_H
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#define __ASM_ARCH_PWMCLK_H __FILE__
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/**
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* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
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* @cfg: The timer TCFG1 register bits shifted down to 0.
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*
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* Return true if the given configuration from TCFG1 is a TCLK instead
|
||||
* any of the TDIV clocks.
|
||||
*/
|
||||
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
|
||||
{
|
||||
return tcfg == S3C2410_TCFG1_MUX_TCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
|
||||
* @tcfg1: The tcfg1 setting, shifted down.
|
||||
*
|
||||
* Get the divisor value for the given tcfg1 setting. We assume the
|
||||
* caller has already checked to see if this is not a TCLK source.
|
||||
*/
|
||||
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
|
||||
{
|
||||
return 1 << (1 + tcfg1);
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
|
||||
*
|
||||
* Return true if we have a /1 in the tdiv setting.
|
||||
*/
|
||||
static inline unsigned int pwm_tdiv_has_div1(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
|
||||
* @div: The divisor to calculate the bit information for.
|
||||
*
|
||||
* Turn a divisor into the necessary bit field for TCFG1.
|
||||
*/
|
||||
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
|
||||
{
|
||||
return ilog2(div) - 1;
|
||||
}
|
||||
|
||||
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
|
||||
|
||||
#endif /* __ASM_ARCH_PWMCLK_H */
|
||||
103
arch/arm/mach-s5p6442/include/mach/regs-clock.h
Normal file
103
arch/arm/mach-s5p6442/include/mach/regs-clock.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5P6442 - Clock register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_CLOCK_H
|
||||
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
|
||||
|
||||
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
|
||||
#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
|
||||
#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
|
||||
#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
|
||||
|
||||
#define S5P_APLL_CON S5P_CLKREG(0x100)
|
||||
#define S5P_MPLL_CON S5P_CLKREG(0x108)
|
||||
#define S5P_EPLL_CON S5P_CLKREG(0x110)
|
||||
#define S5P_VPLL_CON S5P_CLKREG(0x120)
|
||||
|
||||
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
|
||||
#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
|
||||
#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
|
||||
#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
|
||||
#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
|
||||
#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
|
||||
#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
|
||||
|
||||
#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
|
||||
#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
|
||||
|
||||
#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
|
||||
#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
|
||||
#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
|
||||
#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
|
||||
#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
|
||||
#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
|
||||
#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
|
||||
|
||||
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
|
||||
|
||||
/* CLK_OUT */
|
||||
#define S5P_CLK_OUT_SHIFT (12)
|
||||
#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT)
|
||||
#define S5P_CLK_OUT S5P_CLKREG(0x500)
|
||||
|
||||
#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000)
|
||||
#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004)
|
||||
|
||||
#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100)
|
||||
#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104)
|
||||
|
||||
#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
|
||||
|
||||
/* Register Bit definition */
|
||||
#define S5P_EPLL_EN (1<<31)
|
||||
#define S5P_EPLL_MASK 0xffffffff
|
||||
#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
|
||||
|
||||
/* CLKDIV0 */
|
||||
#define S5P_CLKDIV0_APLL_SHIFT (0)
|
||||
#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
|
||||
#define S5P_CLKDIV0_A2M_SHIFT (4)
|
||||
#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
|
||||
#define S5P_CLKDIV0_D0CLK_SHIFT (16)
|
||||
#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
|
||||
#define S5P_CLKDIV0_P0CLK_SHIFT (20)
|
||||
#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
|
||||
#define S5P_CLKDIV0_D1CLK_SHIFT (24)
|
||||
#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
|
||||
#define S5P_CLKDIV0_P1CLK_SHIFT (28)
|
||||
#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
|
||||
|
||||
/* Clock MUX status Registers */
|
||||
#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0)
|
||||
#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4)
|
||||
#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8)
|
||||
#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12)
|
||||
#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16)
|
||||
#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20)
|
||||
#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24)
|
||||
#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24)
|
||||
#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
|
||||
#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28)
|
||||
#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_CLOCK_H */
|
||||
26
arch/arm/mach-s5p6442/include/mach/tick.h
Normal file
26
arch/arm/mach-s5p6442/include/mach/tick.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/* linux/arch/arm/mach-s5p6442/include/mach/tick.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Based on arch/arm/mach-s3c6400/include/mach/tick.h
|
||||
*
|
||||
* S5P6442 - Timer tick support definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_TICK_H
|
||||
#define __ASM_ARCH_TICK_H __FILE__
|
||||
|
||||
static inline u32 s3c24xx_ostimer_pending(void)
|
||||
{
|
||||
u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
|
||||
return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
|
||||
}
|
||||
|
||||
#define TICK_MAX (0xffffffff)
|
||||
|
||||
#endif /* __ASM_ARCH_TICK_H */
|
||||
Loading…
Reference in a new issue