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serial: 8250_bcm2835aux: Add missing clk_disable_unprepare()
[ Upstream commitb9f1736e47
] The error path when get clock frequency fails in bcm2835aux_serial driver does not correctly disable the clock. This flaw was found using a static analysis tool "Hulk Robot", which reported the following warning when analyzing linux-next/master: drivers/tty/serial/8250/8250_bcm2835aux.c: warning: clk_disable_unprepare_missing.cocci The cocci script checks for the existence of clk_disable_unprepare() paired with clk_prepare_enable(). Add the missing clk_disable_unprepare() to the error path. Fixes:fcc446c8aa
("serial: 8250_bcm2835aux: Add ACPI support") Reported-by: Hulk Robot <hulkci@huawei.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Guo Mengqi <guomengqi3@huawei.com> Link: https://lore.kernel.org/r/20220715023312.37808-1-guomengqi3@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 4 additions and 2 deletions
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@ -166,8 +166,10 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev)
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uartclk = clk_get_rate(data->clk);
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if (!uartclk) {
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ret = device_property_read_u32(&pdev->dev, "clock-frequency", &uartclk);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "could not get clk rate\n");
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if (ret) {
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dev_err_probe(&pdev->dev, ret, "could not get clk rate\n");
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goto dis_clk;
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}
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}
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/* the HW-clock divider for bcm2835aux is 8,
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