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drm/radeon: SI tiling fixes for display
- Use the correct union for getting the tiling info - Properly init the PIPE_CONFIG field for SI Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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fb09185a88
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2 changed files with 81 additions and 1 deletions
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@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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}
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if (tiling_flags & RADEON_TILING_MACRO) {
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if (rdev->family >= CHIP_CAYMAN)
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if (rdev->family >= CHIP_TAHITI)
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tmp = rdev->config.si.tile_config;
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else if (rdev->family >= CHIP_CAYMAN)
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tmp = rdev->config.cayman.tile_config;
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else
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tmp = rdev->config.evergreen.tile_config;
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@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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} else if (tiling_flags & RADEON_TILING_MICRO)
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fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
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if ((rdev->family == CHIP_TAHITI) ||
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(rdev->family == CHIP_PITCAIRN))
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fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
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else if (rdev->family == CHIP_VERDE)
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fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
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switch (radeon_crtc->crtc_id) {
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case 0:
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WREG32(AVIVO_D1VGA_CONTROL, 0);
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@ -30,4 +30,76 @@
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#define SI_DC_GPIO_HPD_EN 0x65b8
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#define SI_DC_GPIO_HPD_Y 0x65bc
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#define SI_GRPH_CONTROL 0x6804
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# define SI_GRPH_DEPTH(x) (((x) & 0x3) << 0)
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# define SI_GRPH_DEPTH_8BPP 0
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# define SI_GRPH_DEPTH_16BPP 1
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# define SI_GRPH_DEPTH_32BPP 2
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# define SI_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
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# define SI_ADDR_SURF_2_BANK 0
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# define SI_ADDR_SURF_4_BANK 1
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# define SI_ADDR_SURF_8_BANK 2
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# define SI_ADDR_SURF_16_BANK 3
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# define SI_GRPH_Z(x) (((x) & 0x3) << 4)
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# define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
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# define SI_ADDR_SURF_BANK_WIDTH_1 0
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# define SI_ADDR_SURF_BANK_WIDTH_2 1
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# define SI_ADDR_SURF_BANK_WIDTH_4 2
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# define SI_ADDR_SURF_BANK_WIDTH_8 3
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# define SI_GRPH_FORMAT(x) (((x) & 0x7) << 8)
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/* 8 BPP */
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# define SI_GRPH_FORMAT_INDEXED 0
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/* 16 BPP */
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# define SI_GRPH_FORMAT_ARGB1555 0
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# define SI_GRPH_FORMAT_ARGB565 1
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# define SI_GRPH_FORMAT_ARGB4444 2
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# define SI_GRPH_FORMAT_AI88 3
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# define SI_GRPH_FORMAT_MONO16 4
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# define SI_GRPH_FORMAT_BGRA5551 5
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/* 32 BPP */
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# define SI_GRPH_FORMAT_ARGB8888 0
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# define SI_GRPH_FORMAT_ARGB2101010 1
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# define SI_GRPH_FORMAT_32BPP_DIG 2
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# define SI_GRPH_FORMAT_8B_ARGB2101010 3
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# define SI_GRPH_FORMAT_BGRA1010102 4
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# define SI_GRPH_FORMAT_8B_BGRA1010102 5
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# define SI_GRPH_FORMAT_RGB111110 6
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# define SI_GRPH_FORMAT_BGR101111 7
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# define SI_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
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# define SI_ADDR_SURF_BANK_HEIGHT_1 0
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# define SI_ADDR_SURF_BANK_HEIGHT_2 1
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# define SI_ADDR_SURF_BANK_HEIGHT_4 2
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# define SI_ADDR_SURF_BANK_HEIGHT_8 3
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# define SI_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
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# define SI_ADDR_SURF_TILE_SPLIT_64B 0
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# define SI_ADDR_SURF_TILE_SPLIT_128B 1
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# define SI_ADDR_SURF_TILE_SPLIT_256B 2
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# define SI_ADDR_SURF_TILE_SPLIT_512B 3
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# define SI_ADDR_SURF_TILE_SPLIT_1KB 4
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# define SI_ADDR_SURF_TILE_SPLIT_2KB 5
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# define SI_ADDR_SURF_TILE_SPLIT_4KB 6
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# define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
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# define SI_ADDR_SURF_MACRO_TILE_ASPECT_1 0
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# define SI_ADDR_SURF_MACRO_TILE_ASPECT_2 1
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# define SI_ADDR_SURF_MACRO_TILE_ASPECT_4 2
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# define SI_ADDR_SURF_MACRO_TILE_ASPECT_8 3
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# define SI_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
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# define SI_GRPH_ARRAY_LINEAR_GENERAL 0
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# define SI_GRPH_ARRAY_LINEAR_ALIGNED 1
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# define SI_GRPH_ARRAY_1D_TILED_THIN1 2
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# define SI_GRPH_ARRAY_2D_TILED_THIN1 4
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# define SI_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
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# define SI_ADDR_SURF_P2 0
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# define SI_ADDR_SURF_P4_8x16 4
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# define SI_ADDR_SURF_P4_16x16 5
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# define SI_ADDR_SURF_P4_16x32 6
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# define SI_ADDR_SURF_P4_32x32 7
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# define SI_ADDR_SURF_P8_16x16_8x16 8
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# define SI_ADDR_SURF_P8_16x32_8x16 9
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# define SI_ADDR_SURF_P8_32x32_8x16 10
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# define SI_ADDR_SURF_P8_16x32_16x16 11
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# define SI_ADDR_SURF_P8_32x32_16x16 12
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# define SI_ADDR_SURF_P8_32x32_16x32 13
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# define SI_ADDR_SURF_P8_32x64_32x32 14
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#endif
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