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dmaengine: dw-edma: Use non-atomic io-64 methods
Instead of splitting 64-bits IOs up into two 32-bits ones, use the existing non-atomic readq()/writeq() functions. By doing so we can discard CONFIG_64BIT #ifdefs from the code. Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Vinod Koul <vkoul@kernel.org>
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5fdca4a995
commit
b73bdc5054
1 changed files with 6 additions and 26 deletions
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@ -8,6 +8,8 @@
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#include <linux/bitfield.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "dw-edma-core.h"
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#include "dw-edma-v0-core.h"
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#include "dw-edma-v0-regs.h"
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@ -53,8 +55,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
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SET_32(dw, rd_##name, value); \
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} while (0)
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#ifdef CONFIG_64BIT
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#define SET_64(dw, name, value) \
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writeq(value, &(__dw_regs(dw)->name))
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@ -80,8 +80,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
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SET_64(dw, rd_##name, value); \
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} while (0)
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#endif /* CONFIG_64BIT */
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#define SET_COMPAT(dw, name, value) \
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writel(value, &(__dw_regs(dw)->type.unroll.name))
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@ -164,8 +162,6 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
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#define SET_LL_32(ll, value) \
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writel(value, ll)
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#ifdef CONFIG_64BIT
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static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
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u64 value, void __iomem *addr)
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{
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@ -225,8 +221,6 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
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#define SET_LL_64(ll, value) \
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writeq(value, ll)
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#endif /* CONFIG_64BIT */
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/* eDMA management callbacks */
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void dw_edma_v0_core_off(struct dw_edma *dw)
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{
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@ -325,19 +319,10 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
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/* Transfer size */
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SET_LL_32(&lli[i].transfer_size, child->sz);
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/* SAR */
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#ifdef CONFIG_64BIT
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SET_LL_64(&lli[i].sar.reg, child->sar);
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#else /* CONFIG_64BIT */
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SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar));
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SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar));
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#endif /* CONFIG_64BIT */
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SET_LL_64(&lli[i].sar.reg, child->sar);
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/* DAR */
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#ifdef CONFIG_64BIT
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SET_LL_64(&lli[i].dar.reg, child->dar);
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#else /* CONFIG_64BIT */
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SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar));
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SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar));
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#endif /* CONFIG_64BIT */
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SET_LL_64(&lli[i].dar.reg, child->dar);
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i++;
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}
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@ -349,12 +334,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
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/* Channel control */
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SET_LL_32(&llp->control, control);
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/* Linked list */
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#ifdef CONFIG_64BIT
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SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
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#else /* CONFIG_64BIT */
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SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr));
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SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr));
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#endif /* CONFIG_64BIT */
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SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
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}
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void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
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