MIPS: Alchemy: Fix AU1100 interrupt numbers off-by-one

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss 2009-03-31 18:51:27 +02:00 committed by Ralf Baechle
parent bcf11801e7
commit b7863ee144

View file

@ -715,7 +715,7 @@ enum soc_au1500_ints {
#ifdef CONFIG_SOC_AU1100
enum soc_au1100_ints {
AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
AU1100_UART0_INT,
AU1100_UART0_INT = AU1100_FIRST_INT,
AU1100_UART1_INT,
AU1100_SD_INT,
AU1100_UART3_INT,