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[ARM] 4902/1: [AT91] SAM9/CAP9 memory controller header
The AT91CAP9 processor includes the same Static Memory Controller (SMC) peripheral as the SAM9 processors, but replaces the SDRAM Controller with a DDR/SDR Controller (DDRSDRC). This patch splits the existing include/asm-arm/arch-at91/at91sam926x_mc.h into at91sam9_sdramc.h and at91sam9_smc.h. It also adds an at91cap9_ddrsdr.h for the DDRSDRC controller. Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
3ad0920d7b
commit
b78eabde89
13 changed files with 188 additions and 73 deletions
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@ -23,8 +23,8 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91cap9.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91cap9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -19,8 +19,8 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -24,7 +24,7 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9261.h>
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#include <asm/arch/at91sam9261_matrix.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -22,8 +22,8 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9263_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -20,7 +20,7 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91sam9rl_matrix.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -45,7 +45,7 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91cap9_matrix.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -37,7 +37,7 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -44,7 +44,7 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -43,7 +43,7 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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@ -29,7 +29,7 @@
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include "generic.h"
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100
include/asm-arm/arch-at91/at91cap9_ddrsdr.h
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100
include/asm-arm/arch-at91/at91cap9_ddrsdr.h
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/*
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* include/asm-arm/arch-at91/at91cap9_ddrsdr.h
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*
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* DDR/SDR Controller (DDRSDRC) - System peripherals registers.
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* Based on AT91CAP9 datasheet revision B.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91CAP9_DDRSDR_H
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#define AT91CAP9_DDRSDR_H
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#define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */
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#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
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#define AT91_DDRSDRC_MODE_NORMAL 0
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#define AT91_DDRSDRC_MODE_NOP 1
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#define AT91_DDRSDRC_MODE_PRECHARGE 2
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#define AT91_DDRSDRC_MODE_LMR 3
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#define AT91_DDRSDRC_MODE_REFRESH 4
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#define AT91_DDRSDRC_MODE_EXT_LMR 5
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#define AT91_DDRSDRC_MODE_DEEP 6
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#define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */
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#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */
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#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
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#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
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#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
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#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
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#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
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#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
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#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
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#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
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#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
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#define AT91_DDRSDRC_NR_11 (0 << 2)
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#define AT91_DDRSDRC_NR_12 (1 << 2)
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#define AT91_DDRSDRC_NR_13 (2 << 2)
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#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
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#define AT91_DDRSDRC_CAS_2 (2 << 4)
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#define AT91_DDRSDRC_CAS_3 (3 << 4)
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#define AT91_DDRSDRC_CAS_25 (6 << 4)
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#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
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#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
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#define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */
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#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
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#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
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#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
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#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
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#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
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#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
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#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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#define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */
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#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
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#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
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#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
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#define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */
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#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_DDRSDRC_LPCB_DISABLE 0
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#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
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#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
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#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
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#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
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#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */
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#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
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#define AT91_DDRSDRC_MD_SDR 0
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#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
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#define AT91_DDRSDRC_MD_DDR 2
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#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
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#define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */
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#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
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#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
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#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
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#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
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#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
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#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
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#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
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#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
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#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
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#endif
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/*
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* include/asm-arm/arch-at91/at91sam926x_mc.h
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* include/asm-arm/arch-at91/at91sam9_sdramc.h
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*
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* Memory Controllers (SMC, SDRAMC) - System peripherals registers.
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* SDRAM Controllers (SDRAMC) - System peripherals registers.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* (at your option) any later version.
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*/
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#ifndef AT91SAM926x_MC_H
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#define AT91SAM926x_MC_H
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#ifndef AT91SAM9_SDRAMC_H
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#define AT91SAM9_SDRAMC_H
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/* SDRAM Controller (SDRAMC) registers */
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#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
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#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
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#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
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#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
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/* Static Memory Controller (SMC) registers */
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#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
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#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
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#define AT91_SMC_NWESETUP_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
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#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
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#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
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#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
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#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
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#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
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#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
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#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
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#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
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#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
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#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
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#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
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#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
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#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
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#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
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#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
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#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
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#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
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#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
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#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
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#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
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#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
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#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
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#define AT91_SMC_EXNWMODE_READY (3 << 4)
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#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
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#define AT91_SMC_BAT_SELECT (0 << 8)
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#define AT91_SMC_BAT_WRITE (1 << 8)
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#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
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#define AT91_SMC_DBW_8 (0 << 12)
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#define AT91_SMC_DBW_16 (1 << 12)
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#define AT91_SMC_DBW_32 (2 << 12)
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#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
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#define AT91_SMC_TDF_(x) ((x) << 16)
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#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
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#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
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#define AT91_SMC_PS (3 << 28) /* Page Size */
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#define AT91_SMC_PS_4 (0 << 28)
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#define AT91_SMC_PS_8 (1 << 28)
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#define AT91_SMC_PS_16 (2 << 28)
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#define AT91_SMC_PS_32 (3 << 28)
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#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
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#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
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#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
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#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
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#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
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#endif
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#endif
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include/asm-arm/arch-at91/at91sam9_smc.h
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73
include/asm-arm/arch-at91/at91sam9_smc.h
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/*
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* include/asm-arm/arch-at91/at91sam9_smc.h
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*
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* Static Memory Controllers (SMC) - System peripherals registers.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9_SMC_H
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#define AT91SAM9_SMC_H
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#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
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#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
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#define AT91_SMC_NWESETUP_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
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#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
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#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
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#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
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#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
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#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
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#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
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#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
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#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
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#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
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#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
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#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
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#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
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#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
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#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
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#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
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#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
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#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
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#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
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#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
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#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
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#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
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#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
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#define AT91_SMC_EXNWMODE_READY (3 << 4)
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#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
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#define AT91_SMC_BAT_SELECT (0 << 8)
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#define AT91_SMC_BAT_WRITE (1 << 8)
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#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
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#define AT91_SMC_DBW_8 (0 << 12)
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#define AT91_SMC_DBW_16 (1 << 12)
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#define AT91_SMC_DBW_32 (2 << 12)
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#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
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#define AT91_SMC_TDF_(x) ((x) << 16)
|
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#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
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#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
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#define AT91_SMC_PS (3 << 28) /* Page Size */
|
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#define AT91_SMC_PS_4 (0 << 28)
|
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#define AT91_SMC_PS_8 (1 << 28)
|
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#define AT91_SMC_PS_16 (2 << 28)
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#define AT91_SMC_PS_32 (3 << 28)
|
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|
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#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
|
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#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
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#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
|
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#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
|
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#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
|
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#endif
|
||||
|
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#endif
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Loading…
Reference in a new issue