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clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock
To achieve CPR-Hardened functionality this clock must be on: add it in order to be able to get it managed by the CPR3 driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-5-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1 changed files with 20 additions and 0 deletions
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@ -2160,6 +2160,25 @@ static struct clk_branch gcc_hmss_trig_clk = {
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},
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},
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};
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};
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static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
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F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
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F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 hmss_gpll0_clk_src = {
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.cmd_rcgr = 0x4805c,
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.hid_width = 5,
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.parent_map = gcc_parent_map_1,
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.freq_tbl = ftbl_hmss_gpll0_clk_src,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "hmss_gpll0_clk_src",
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.parent_names = gcc_parent_names_1,
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.num_parents = ARRAY_SIZE(gcc_parent_names_1),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
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static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
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.halt_reg = 0x9004,
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.halt_reg = 0x9004,
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.halt_check = BRANCH_HALT,
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.halt_check = BRANCH_HALT,
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@ -2961,6 +2980,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
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[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
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[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
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[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
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[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
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[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
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[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
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[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
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};
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};
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static struct gdsc *gcc_msm8998_gdscs[] = {
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static struct gdsc *gcc_msm8998_gdscs[] = {
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