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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 10:57:46 +00:00
b43: Fix DMA for 30/32-bit DMA engines
This checks if the DMA address is bigger than what the controller can manage. It will reallocate the buffers in the GFP_DMA zone in that case. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
532031d7f4
commit
b79caa68c0
2 changed files with 99 additions and 58 deletions
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@ -337,7 +337,7 @@ static inline int txring_to_priority(struct b43_dmaring *ring)
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return idx_to_prio[index];
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return idx_to_prio[index];
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}
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}
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u16 b43_dmacontroller_base(int dma64bit, int controller_idx)
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static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
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{
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{
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static const u16 map64[] = {
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static const u16 map64[] = {
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B43_MMIO_DMA64_BASE0,
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B43_MMIO_DMA64_BASE0,
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@ -356,7 +356,7 @@ u16 b43_dmacontroller_base(int dma64bit, int controller_idx)
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B43_MMIO_DMA32_BASE5,
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B43_MMIO_DMA32_BASE5,
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};
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};
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if (dma64bit) {
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if (type == B43_DMA_64BIT) {
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B43_WARN_ON(!(controller_idx >= 0 &&
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B43_WARN_ON(!(controller_idx >= 0 &&
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controller_idx < ARRAY_SIZE(map64)));
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controller_idx < ARRAY_SIZE(map64)));
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return map64[controller_idx];
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return map64[controller_idx];
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@ -437,7 +437,7 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
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* 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
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* 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
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* which accounts for the GFP_DMA flag below.
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* which accounts for the GFP_DMA flag below.
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*/
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*/
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if (ring->dma64)
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if (ring->type == B43_DMA_64BIT)
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flags |= GFP_DMA;
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flags |= GFP_DMA;
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ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
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ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
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&(ring->dmabase), flags);
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&(ring->dmabase), flags);
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@ -459,7 +459,8 @@ static void free_ringmemory(struct b43_dmaring *ring)
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}
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}
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/* Reset the RX DMA channel */
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/* Reset the RX DMA channel */
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int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
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enum b43_dmatype type)
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{
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{
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int i;
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int i;
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u32 value;
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u32 value;
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@ -467,12 +468,13 @@ int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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might_sleep();
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might_sleep();
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offset = dma64 ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
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offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
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b43_write32(dev, mmio_base + offset, 0);
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b43_write32(dev, mmio_base + offset, 0);
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 10; i++) {
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offset = dma64 ? B43_DMA64_RXSTATUS : B43_DMA32_RXSTATUS;
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offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
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B43_DMA32_RXSTATUS;
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value = b43_read32(dev, mmio_base + offset);
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value = b43_read32(dev, mmio_base + offset);
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if (dma64) {
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if (type == B43_DMA_64BIT) {
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value &= B43_DMA64_RXSTAT;
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value &= B43_DMA64_RXSTAT;
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if (value == B43_DMA64_RXSTAT_DISABLED) {
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if (value == B43_DMA64_RXSTAT_DISABLED) {
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i = -1;
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i = -1;
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@ -496,7 +498,8 @@ int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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}
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}
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/* Reset the TX DMA channel */
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/* Reset the TX DMA channel */
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int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
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enum b43_dmatype type)
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{
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{
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int i;
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int i;
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u32 value;
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u32 value;
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@ -505,9 +508,10 @@ int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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might_sleep();
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might_sleep();
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 10; i++) {
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offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
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offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
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B43_DMA32_TXSTATUS;
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value = b43_read32(dev, mmio_base + offset);
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value = b43_read32(dev, mmio_base + offset);
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if (dma64) {
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if (type == B43_DMA_64BIT) {
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value &= B43_DMA64_TXSTAT;
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value &= B43_DMA64_TXSTAT;
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if (value == B43_DMA64_TXSTAT_DISABLED ||
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if (value == B43_DMA64_TXSTAT_DISABLED ||
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value == B43_DMA64_TXSTAT_IDLEWAIT ||
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value == B43_DMA64_TXSTAT_IDLEWAIT ||
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@ -522,12 +526,13 @@ int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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}
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}
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msleep(1);
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msleep(1);
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}
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}
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offset = dma64 ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
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offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
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b43_write32(dev, mmio_base + offset, 0);
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b43_write32(dev, mmio_base + offset, 0);
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 10; i++) {
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offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
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offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
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B43_DMA32_TXSTATUS;
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value = b43_read32(dev, mmio_base + offset);
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value = b43_read32(dev, mmio_base + offset);
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if (dma64) {
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if (type == B43_DMA_64BIT) {
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value &= B43_DMA64_TXSTAT;
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value &= B43_DMA64_TXSTAT;
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if (value == B43_DMA64_TXSTAT_DISABLED) {
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if (value == B43_DMA64_TXSTAT_DISABLED) {
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i = -1;
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i = -1;
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@ -552,6 +557,33 @@ int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
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return 0;
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return 0;
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}
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}
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/* Check if a DMA mapping address is invalid. */
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static bool b43_dma_mapping_error(struct b43_dmaring *ring,
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dma_addr_t addr,
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size_t buffersize)
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{
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if (unlikely(dma_mapping_error(addr)))
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return 1;
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switch (ring->type) {
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case B43_DMA_30BIT:
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if ((u64)addr + buffersize > (1ULL << 30))
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return 1;
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break;
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case B43_DMA_32BIT:
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if ((u64)addr + buffersize > (1ULL << 32))
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return 1;
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break;
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case B43_DMA_64BIT:
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/* Currently we can't have addresses beyond
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* 64bit in the kernel. */
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break;
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}
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/* The address is OK. */
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return 0;
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}
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static int setup_rx_descbuffer(struct b43_dmaring *ring,
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static int setup_rx_descbuffer(struct b43_dmaring *ring,
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struct b43_dmadesc_generic *desc,
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struct b43_dmadesc_generic *desc,
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struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
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struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
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@ -567,7 +599,7 @@ static int setup_rx_descbuffer(struct b43_dmaring *ring,
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if (unlikely(!skb))
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if (unlikely(!skb))
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return -ENOMEM;
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return -ENOMEM;
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dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
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dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
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if (dma_mapping_error(dmaaddr)) {
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if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) {
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/* ugh. try to realloc in zone_dma */
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/* ugh. try to realloc in zone_dma */
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gfp_flags |= GFP_DMA;
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gfp_flags |= GFP_DMA;
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@ -580,7 +612,7 @@ static int setup_rx_descbuffer(struct b43_dmaring *ring,
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ring->rx_buffersize, 0);
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ring->rx_buffersize, 0);
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}
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}
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if (dma_mapping_error(dmaaddr)) {
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if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) {
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dev_kfree_skb_any(skb);
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dev_kfree_skb_any(skb);
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return -EIO;
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return -EIO;
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}
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}
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@ -645,7 +677,7 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
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u32 trans = ssb_dma_translation(ring->dev->dev);
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u32 trans = ssb_dma_translation(ring->dev->dev);
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if (ring->tx) {
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if (ring->tx) {
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if (ring->dma64) {
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if (ring->type == B43_DMA_64BIT) {
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u64 ringbase = (u64) (ring->dmabase);
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u64 ringbase = (u64) (ring->dmabase);
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addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
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addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
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@ -677,7 +709,7 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
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err = alloc_initial_descbuffers(ring);
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err = alloc_initial_descbuffers(ring);
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if (err)
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if (err)
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goto out;
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goto out;
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if (ring->dma64) {
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if (ring->type == B43_DMA_64BIT) {
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u64 ringbase = (u64) (ring->dmabase);
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u64 ringbase = (u64) (ring->dmabase);
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addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
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addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
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@ -722,16 +754,16 @@ static void dmacontroller_cleanup(struct b43_dmaring *ring)
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{
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{
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if (ring->tx) {
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if (ring->tx) {
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b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
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b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
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ring->dma64);
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ring->type);
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if (ring->dma64) {
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if (ring->type == B43_DMA_64BIT) {
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b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
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b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
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b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
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b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
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} else
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} else
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b43_dma_write(ring, B43_DMA32_TXRING, 0);
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b43_dma_write(ring, B43_DMA32_TXRING, 0);
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} else {
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} else {
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b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
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b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
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ring->dma64);
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ring->type);
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if (ring->dma64) {
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if (ring->type == B43_DMA_64BIT) {
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b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
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b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
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b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
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b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
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} else
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} else
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@ -786,7 +818,8 @@ static u64 supported_dma_mask(struct b43_wldev *dev)
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static
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static
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struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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int controller_index,
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int controller_index,
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int for_tx, int dma64)
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int for_tx,
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enum b43_dmatype type)
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{
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{
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struct b43_dmaring *ring;
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struct b43_dmaring *ring;
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int err;
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int err;
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@ -796,6 +829,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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ring = kzalloc(sizeof(*ring), GFP_KERNEL);
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ring = kzalloc(sizeof(*ring), GFP_KERNEL);
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if (!ring)
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if (!ring)
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goto out;
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goto out;
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ring->type = type;
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nr_slots = B43_RXRING_SLOTS;
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nr_slots = B43_RXRING_SLOTS;
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if (for_tx)
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if (for_tx)
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@ -818,7 +852,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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b43_txhdr_size(dev),
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b43_txhdr_size(dev),
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DMA_TO_DEVICE);
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DMA_TO_DEVICE);
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if (dma_mapping_error(dma_test)) {
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if (b43_dma_mapping_error(ring, dma_test, b43_txhdr_size(dev))) {
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/* ugh realloc */
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/* ugh realloc */
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kfree(ring->txhdr_cache);
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kfree(ring->txhdr_cache);
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ring->txhdr_cache = kcalloc(nr_slots,
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ring->txhdr_cache = kcalloc(nr_slots,
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@ -832,7 +866,8 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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b43_txhdr_size(dev),
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b43_txhdr_size(dev),
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DMA_TO_DEVICE);
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DMA_TO_DEVICE);
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if (dma_mapping_error(dma_test))
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if (b43_dma_mapping_error(ring, dma_test,
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b43_txhdr_size(dev)))
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goto err_kfree_txhdr_cache;
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goto err_kfree_txhdr_cache;
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}
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}
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@ -843,10 +878,9 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
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ring->dev = dev;
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ring->dev = dev;
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ring->nr_slots = nr_slots;
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ring->nr_slots = nr_slots;
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ring->mmio_base = b43_dmacontroller_base(dma64, controller_index);
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ring->mmio_base = b43_dmacontroller_base(type, controller_index);
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ring->index = controller_index;
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ring->index = controller_index;
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ring->dma64 = !!dma64;
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if (type == B43_DMA_64BIT)
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if (dma64)
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ring->ops = &dma64_ops;
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ring->ops = &dma64_ops;
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else
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else
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ring->ops = &dma32_ops;
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ring->ops = &dma32_ops;
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@ -896,8 +930,8 @@ static void b43_destroy_dmaring(struct b43_dmaring *ring)
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if (!ring)
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if (!ring)
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return;
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return;
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b43dbg(ring->dev->wl, "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
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b43dbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots: %d/%d\n",
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(ring->dma64) ? "64" : "32",
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(unsigned int)(ring->type),
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ring->mmio_base,
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ring->mmio_base,
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(ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots);
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(ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots);
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/* Device IRQs are disabled prior entering this function,
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/* Device IRQs are disabled prior entering this function,
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@ -941,12 +975,22 @@ int b43_dma_init(struct b43_wldev *dev)
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struct b43_dmaring *ring;
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struct b43_dmaring *ring;
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int err;
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int err;
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u64 dmamask;
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u64 dmamask;
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int dma64 = 0;
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enum b43_dmatype type;
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dmamask = supported_dma_mask(dev);
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dmamask = supported_dma_mask(dev);
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if (dmamask == DMA_64BIT_MASK)
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switch (dmamask) {
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dma64 = 1;
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default:
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B43_WARN_ON(1);
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case DMA_30BIT_MASK:
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type = B43_DMA_30BIT;
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break;
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case DMA_32BIT_MASK:
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type = B43_DMA_32BIT;
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break;
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case DMA_64BIT_MASK:
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type = B43_DMA_64BIT;
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break;
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}
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err = ssb_dma_set_mask(dev->dev, dmamask);
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err = ssb_dma_set_mask(dev->dev, dmamask);
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if (err) {
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if (err) {
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b43err(dev->wl, "The machine/kernel does not support "
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b43err(dev->wl, "The machine/kernel does not support "
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@ -958,52 +1002,51 @@ int b43_dma_init(struct b43_wldev *dev)
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err = -ENOMEM;
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err = -ENOMEM;
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/* setup TX DMA channels. */
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/* setup TX DMA channels. */
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ring = b43_setup_dmaring(dev, 0, 1, dma64);
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ring = b43_setup_dmaring(dev, 0, 1, type);
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if (!ring)
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if (!ring)
|
||||||
goto out;
|
goto out;
|
||||||
dma->tx_ring0 = ring;
|
dma->tx_ring0 = ring;
|
||||||
|
|
||||||
ring = b43_setup_dmaring(dev, 1, 1, dma64);
|
ring = b43_setup_dmaring(dev, 1, 1, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_tx0;
|
goto err_destroy_tx0;
|
||||||
dma->tx_ring1 = ring;
|
dma->tx_ring1 = ring;
|
||||||
|
|
||||||
ring = b43_setup_dmaring(dev, 2, 1, dma64);
|
ring = b43_setup_dmaring(dev, 2, 1, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_tx1;
|
goto err_destroy_tx1;
|
||||||
dma->tx_ring2 = ring;
|
dma->tx_ring2 = ring;
|
||||||
|
|
||||||
ring = b43_setup_dmaring(dev, 3, 1, dma64);
|
ring = b43_setup_dmaring(dev, 3, 1, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_tx2;
|
goto err_destroy_tx2;
|
||||||
dma->tx_ring3 = ring;
|
dma->tx_ring3 = ring;
|
||||||
|
|
||||||
ring = b43_setup_dmaring(dev, 4, 1, dma64);
|
ring = b43_setup_dmaring(dev, 4, 1, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_tx3;
|
goto err_destroy_tx3;
|
||||||
dma->tx_ring4 = ring;
|
dma->tx_ring4 = ring;
|
||||||
|
|
||||||
ring = b43_setup_dmaring(dev, 5, 1, dma64);
|
ring = b43_setup_dmaring(dev, 5, 1, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_tx4;
|
goto err_destroy_tx4;
|
||||||
dma->tx_ring5 = ring;
|
dma->tx_ring5 = ring;
|
||||||
|
|
||||||
/* setup RX DMA channels. */
|
/* setup RX DMA channels. */
|
||||||
ring = b43_setup_dmaring(dev, 0, 0, dma64);
|
ring = b43_setup_dmaring(dev, 0, 0, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_tx5;
|
goto err_destroy_tx5;
|
||||||
dma->rx_ring0 = ring;
|
dma->rx_ring0 = ring;
|
||||||
|
|
||||||
if (dev->dev->id.revision < 5) {
|
if (dev->dev->id.revision < 5) {
|
||||||
ring = b43_setup_dmaring(dev, 3, 0, dma64);
|
ring = b43_setup_dmaring(dev, 3, 0, type);
|
||||||
if (!ring)
|
if (!ring)
|
||||||
goto err_destroy_rx0;
|
goto err_destroy_rx0;
|
||||||
dma->rx_ring3 = ring;
|
dma->rx_ring3 = ring;
|
||||||
}
|
}
|
||||||
|
|
||||||
b43dbg(dev->wl, "%d-bit DMA initialized\n",
|
b43dbg(dev->wl, "%u-bit DMA initialized\n",
|
||||||
(dmamask == DMA_64BIT_MASK) ? 64 :
|
(unsigned int)type);
|
||||||
(dmamask == DMA_32BIT_MASK) ? 32 : 30);
|
|
||||||
err = 0;
|
err = 0;
|
||||||
out:
|
out:
|
||||||
return err;
|
return err;
|
||||||
|
@ -1146,7 +1189,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
|
||||||
|
|
||||||
meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
|
meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
|
||||||
hdrsize, 1);
|
hdrsize, 1);
|
||||||
if (dma_mapping_error(meta_hdr->dmaaddr)) {
|
if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize)) {
|
||||||
ring->current_slot = old_top_slot;
|
ring->current_slot = old_top_slot;
|
||||||
ring->used_slots = old_used_slots;
|
ring->used_slots = old_used_slots;
|
||||||
return -EIO;
|
return -EIO;
|
||||||
|
@ -1165,7 +1208,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
|
||||||
|
|
||||||
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
|
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
|
||||||
/* create a bounce buffer in zone_dma on mapping failure. */
|
/* create a bounce buffer in zone_dma on mapping failure. */
|
||||||
if (dma_mapping_error(meta->dmaaddr)) {
|
if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) {
|
||||||
bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
|
bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
|
||||||
if (!bounce_skb) {
|
if (!bounce_skb) {
|
||||||
ring->current_slot = old_top_slot;
|
ring->current_slot = old_top_slot;
|
||||||
|
@ -1179,7 +1222,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
|
||||||
skb = bounce_skb;
|
skb = bounce_skb;
|
||||||
meta->skb = skb;
|
meta->skb = skb;
|
||||||
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
|
meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
|
||||||
if (dma_mapping_error(meta->dmaaddr)) {
|
if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) {
|
||||||
ring->current_slot = old_top_slot;
|
ring->current_slot = old_top_slot;
|
||||||
ring->used_slots = old_used_slots;
|
ring->used_slots = old_used_slots;
|
||||||
err = -EIO;
|
err = -EIO;
|
||||||
|
|
|
@ -203,6 +203,12 @@ struct b43_dma_ops {
|
||||||
void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
|
void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum b43_dmatype {
|
||||||
|
B43_DMA_30BIT = 30,
|
||||||
|
B43_DMA_32BIT = 32,
|
||||||
|
B43_DMA_64BIT = 64,
|
||||||
|
};
|
||||||
|
|
||||||
struct b43_dmaring {
|
struct b43_dmaring {
|
||||||
/* Lowlevel DMA ops. */
|
/* Lowlevel DMA ops. */
|
||||||
const struct b43_dma_ops *ops;
|
const struct b43_dma_ops *ops;
|
||||||
|
@ -235,8 +241,8 @@ struct b43_dmaring {
|
||||||
int index;
|
int index;
|
||||||
/* Boolean. Is this a TX ring? */
|
/* Boolean. Is this a TX ring? */
|
||||||
bool tx;
|
bool tx;
|
||||||
/* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
|
/* The type of DMA engine used. */
|
||||||
bool dma64;
|
enum b43_dmatype type;
|
||||||
/* Boolean. Is this ring stopped at ieee80211 level? */
|
/* Boolean. Is this ring stopped at ieee80211 level? */
|
||||||
bool stopped;
|
bool stopped;
|
||||||
/* Lock, only used for TX. */
|
/* Lock, only used for TX. */
|
||||||
|
@ -255,8 +261,7 @@ static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
|
||||||
return b43_read32(ring->dev, ring->mmio_base + offset);
|
return b43_read32(ring->dev, ring->mmio_base + offset);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline
|
static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
|
||||||
void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
|
|
||||||
{
|
{
|
||||||
b43_write32(ring->dev, ring->mmio_base + offset, value);
|
b43_write32(ring->dev, ring->mmio_base + offset, value);
|
||||||
}
|
}
|
||||||
|
@ -264,13 +269,6 @@ static inline
|
||||||
int b43_dma_init(struct b43_wldev *dev);
|
int b43_dma_init(struct b43_wldev *dev);
|
||||||
void b43_dma_free(struct b43_wldev *dev);
|
void b43_dma_free(struct b43_wldev *dev);
|
||||||
|
|
||||||
int b43_dmacontroller_rx_reset(struct b43_wldev *dev,
|
|
||||||
u16 dmacontroller_mmio_base, int dma64);
|
|
||||||
int b43_dmacontroller_tx_reset(struct b43_wldev *dev,
|
|
||||||
u16 dmacontroller_mmio_base, int dma64);
|
|
||||||
|
|
||||||
u16 b43_dmacontroller_base(int dma64bit, int dmacontroller_idx);
|
|
||||||
|
|
||||||
void b43_dma_tx_suspend(struct b43_wldev *dev);
|
void b43_dma_tx_suspend(struct b43_wldev *dev);
|
||||||
void b43_dma_tx_resume(struct b43_wldev *dev);
|
void b43_dma_tx_resume(struct b43_wldev *dev);
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue