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ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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b7a1922814
3 changed files with 11 additions and 8 deletions
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@ -19,6 +19,13 @@ Optional properties:
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- syscon-chipselects: Handle to system control region contains QSPI
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chipselect register and offset of that register.
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NOTE: TI QSPI controller requires different pinmux and IODelay
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paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
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the bootloader (U-Boot). Default configuration only supports Mode-0
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operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
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specified in the slave nodes of TI QSPI controller without appropriate
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modification to bootloader.
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Example:
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For am4372:
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@ -664,15 +664,13 @@ &cpu0 {
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&qspi {
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status = "okay";
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spi-max-frequency = <48000000>;
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spi-max-frequency = <64000000>;
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m25p80@0 {
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compatible = "s25fl256s1";
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spi-max-frequency = <48000000>;
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spi-max-frequency = <64000000>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-cpol;
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spi-cpha;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -681,15 +681,13 @@ &dcan1 {
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&qspi {
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status = "okay";
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spi-max-frequency = <48000000>;
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spi-max-frequency = <64000000>;
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m25p80@0 {
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compatible = "s25fl256s1";
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spi-max-frequency = <48000000>;
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spi-max-frequency = <64000000>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-cpol;
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spi-cpha;
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#address-cells = <1>;
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#size-cells = <1>;
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