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ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz

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According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Vignesh R 2016-04-20 17:03:00 +05:30 committed by Tony Lindgren
parent 626180785f
commit b7a1922814
3 changed files with 11 additions and 8 deletions
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7
Documentation/devicetree/bindings/spi/ti_qspi.txt
View file

@ -19,6 +19,13 @@ Optional properties:
- syscon-chipselects: Handle to system control region contains QSPI
chipselect register and offset of that register.
NOTE: TI QSPI controller requires different pinmux and IODelay
paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
the bootloader (U-Boot). Default configuration only supports Mode-0
operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
specified in the slave nodes of TI QSPI controller without appropriate
modification to bootloader.
Example:
For am4372:

6
arch/arm/boot/dts/dra7-evm.dts
View file

@ -664,15 +664,13 @@ &cpu0 {
&qspi {
status = "okay";
spi-max-frequency = <48000000>;
spi-max-frequency = <64000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <48000000>;
spi-max-frequency = <64000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
#address-cells = <1>;
#size-cells = <1>;

6
arch/arm/boot/dts/dra72-evm-common.dtsi
View file

@ -681,15 +681,13 @@ &dcan1 {
&qspi {
status = "okay";
spi-max-frequency = <48000000>;
spi-max-frequency = <64000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <48000000>;
spi-max-frequency = <64000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
#address-cells = <1>;
#size-cells = <1>;