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pci-v5.1-fixes-3
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAlzK8pkUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vwa1Q/9F/LWkDPI0RHrOYlWNHGwrw+jwL6g XmvBFbuyuqieaTrljtS5PLbfT2DoD0ZISolQqTjDB4KCHr5u0KyaJgUnbHk4c7qq arCOwEC6Ad/xRMmOd3V1qcPAHK8tNigCKOGYOtEk+YfLWfsla7FlqJBtp+5eZ7NZ UnGwkaeOzEDY9JskPhcHcoHkZjILgIU8PQsJMjDkh8iDJpYKIjasWcFoAmLaXZb6 WLha6NO7oZxL3ZX6660K1ah/CxLSx3mgd+BX2KKfucNBmvzu90RuhTRNvegCMm36 BVglWam4vI95a44N/9w+oPao8p5NMnldWbH7/g3iKFPASylLNUDPT/wKdpACYneK ADJmf3+A9OoI7AWEyadR9WvvGuceQ2IoIL0tGI7824HnGwc5KpF+CcFUDTSPRbVO 94H3+q7M9YEA3CvQQkSqEIPtDcrFrO5x+aEijP4EhmE/7IV52VRyEY1IOHr88hzQ umf6TbbxNPaW+g/1IOTSgESSl1nPXKe85Aeb7i4mle9XOp0YIHh44FYyrPoSeysd egdij/9K+EPjlLpLm+X7L/dApwBNt+7dmblxanlilOSaDwkpfZ3yIm0jAgcuXhL6 lXj30vdlCmBiYRV5bMMletrflH29UsEsSpjkW99APU+6Dmx3E2/fWoeEPTkuHw5s bPZ7n6KcJewg8Tg= =ajSb -----END PGP SIGNATURE----- Merge tag 'pci-v5.1-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "I apologize for sending these so late in the cycle. We went back and forth about how to deal with the unexpected logging of intentional link state changes and finally decided to just config them off by default. PCI fixes: - Stop ignoring "pci=disable_acs_redir" parameter (Logan Gunthorpe) - Use shared MSI/MSI-X vector for Link Bandwidth Management (Alex Williamson) - Add Kconfig option for Link Bandwidth notification messages (Keith Busch)" * tag 'pci-v5.1-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI/LINK: Add Kconfig option (default off) PCI/portdrv: Use shared MSI/MSI-X vector for Bandwidth Management PCI: Fix issue with "pci=disable_acs_redir" parameter being ignored
This commit is contained in:
commit
b7a5b22b05
5 changed files with 32 additions and 4 deletions
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@ -6262,8 +6262,7 @@ static int __init pci_setup(char *str)
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} else if (!strncmp(str, "pcie_scan_all", 13)) {
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pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
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} else if (!strncmp(str, "disable_acs_redir=", 18)) {
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disable_acs_redir_param =
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kstrdup(str + 18, GFP_KERNEL);
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disable_acs_redir_param = str + 18;
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} else {
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printk(KERN_ERR "PCI: Unknown option `%s'\n",
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str);
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@ -6274,3 +6273,19 @@ static int __init pci_setup(char *str)
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return 0;
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}
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early_param("pci", pci_setup);
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/*
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* 'disable_acs_redir_param' is initialized in pci_setup(), above, to point
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* to data in the __initdata section which will be freed after the init
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* sequence is complete. We can't allocate memory in pci_setup() because some
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* architectures do not have any memory allocation service available during
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* an early_param() call. So we allocate memory and copy the variable here
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* before the init section is freed.
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*/
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static int __init pci_realloc_setup_params(void)
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{
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disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
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return 0;
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}
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pure_initcall(pci_realloc_setup_params);
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@ -142,3 +142,11 @@ config PCIE_PTM
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This is only useful if you have devices that support PTM, but it
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is safe to enable even if you don't.
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config PCIE_BW
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bool "PCI Express Bandwidth Change Notification"
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depends on PCIEPORTBUS
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help
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This enables PCI Express Bandwidth Change Notification. If
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you know link width or rate changes occur only to correct
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unreliable links, you may answer Y.
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@ -3,7 +3,6 @@
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# Makefile for PCI Express features and port driver
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pcieportdrv-y := portdrv_core.o portdrv_pci.o err.o
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pcieportdrv-y += bw_notification.o
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obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
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@ -13,3 +12,4 @@ obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o
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obj-$(CONFIG_PCIE_PME) += pme.o
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obj-$(CONFIG_PCIE_DPC) += dpc.o
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obj-$(CONFIG_PCIE_PTM) += ptm.o
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obj-$(CONFIG_PCIE_BW) += bw_notification.o
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@ -49,7 +49,11 @@ int pcie_dpc_init(void);
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static inline int pcie_dpc_init(void) { return 0; }
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#endif
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#ifdef CONFIG_PCIE_BW
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int pcie_bandwidth_notification_init(void);
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#else
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static inline int pcie_bandwidth_notification_init(void) { return 0; }
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#endif
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/* Port Type */
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#define PCIE_ANY_PORT (~0)
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@ -55,7 +55,8 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask,
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* 7.8.2, 7.10.10, 7.31.2.
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*/
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if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {
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if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP |
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PCIE_PORT_SERVICE_BWNOTIF)) {
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pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16);
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*pme = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
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nvec = *pme + 1;
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