mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-14 12:37:32 +00:00
Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10' and 'clk-aspeed' into clk-next
* clk-stm32mp1: clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()' clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock clk: stm32mp1: remove ck_apb_dbg clock clk: stm32mp1: set stgen_k clock as critical clk: stm32mp1: add missing tzc2 clock clk: stm32mp1: fix SAI3 & SAI4 clocks clk: stm32mp1: remove unused dfsdm_src[] const clk: stm32mp1: add missing static * clk-samsung: clk: samsung: simplify getting .drvdata * clk-uniphier-mpeg: clk: uniphier: add LD11/LD20 stream demux system clock * clk-stratix10: clk: socfpga: stratix10: suppress unbinding platform's clock driver clk: socfpga: stratix10: use platform driver APIs * clk-aspeed: clk:aspeed: Fix reset bits for PCI/VGA and PECI clk: aspeed: Support second reset register
This commit is contained in:
Stephen Boyd
commit
b7c82cec04
7 changed files with 93 additions and 79 deletions
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@ -16,6 +16,8 @@
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#define ASPEED_NUM_CLKS 35
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#define ASPEED_RESET2_OFFSET 32
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#define ASPEED_RESET_CTRL 0x04
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#define ASPEED_CLK_SELECTION 0x08
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#define ASPEED_CLK_STOP_CTRL 0x0c
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@ -30,6 +32,7 @@
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#define CLKIN_25MHZ_EN BIT(23)
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#define AST2400_CLK_SOURCE_SEL BIT(18)
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#define ASPEED_CLK_SELECTION_2 0xd8
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#define ASPEED_RESET_CTRL2 0xd4
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/* Globally visible clocks */
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static DEFINE_SPINLOCK(aspeed_clk_lock);
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@ -88,7 +91,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
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[ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
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[ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
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[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
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[ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
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[ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
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[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
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[ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
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[ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
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@ -291,47 +294,72 @@ struct aspeed_reset {
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#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
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static const u8 aspeed_resets[] = {
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/* SCU04 resets */
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[ASPEED_RESET_XDMA] = 25,
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[ASPEED_RESET_MCTP] = 24,
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[ASPEED_RESET_ADC] = 23,
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[ASPEED_RESET_JTAG_MASTER] = 22,
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[ASPEED_RESET_MIC] = 18,
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[ASPEED_RESET_PWM] = 9,
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[ASPEED_RESET_PCIVGA] = 8,
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[ASPEED_RESET_PECI] = 10,
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[ASPEED_RESET_I2C] = 2,
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[ASPEED_RESET_AHB] = 1,
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/*
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* SCUD4 resets start at an offset to separate them from
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* the SCU04 resets.
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*/
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[ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5,
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};
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static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct aspeed_reset *ar = to_aspeed_reset(rcdev);
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u32 rst = BIT(aspeed_resets[id]);
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u32 reg = ASPEED_RESET_CTRL;
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u32 bit = aspeed_resets[id];
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return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
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if (bit >= ASPEED_RESET2_OFFSET) {
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bit -= ASPEED_RESET2_OFFSET;
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reg = ASPEED_RESET_CTRL2;
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}
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return regmap_update_bits(ar->map, reg, BIT(bit), 0);
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}
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static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct aspeed_reset *ar = to_aspeed_reset(rcdev);
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u32 rst = BIT(aspeed_resets[id]);
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u32 reg = ASPEED_RESET_CTRL;
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u32 bit = aspeed_resets[id];
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return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
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if (bit >= ASPEED_RESET2_OFFSET) {
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bit -= ASPEED_RESET2_OFFSET;
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reg = ASPEED_RESET_CTRL2;
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}
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return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
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}
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static int aspeed_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct aspeed_reset *ar = to_aspeed_reset(rcdev);
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u32 val, rst = BIT(aspeed_resets[id]);
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int ret;
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u32 reg = ASPEED_RESET_CTRL;
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u32 bit = aspeed_resets[id];
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int ret, val;
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ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
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if (bit >= ASPEED_RESET2_OFFSET) {
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bit -= ASPEED_RESET2_OFFSET;
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reg = ASPEED_RESET_CTRL2;
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}
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ret = regmap_read(ar->map, reg, &val);
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if (ret)
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return ret;
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return !!(val & rst);
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return !!(val & BIT(bit));
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}
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static const struct reset_control_ops aspeed_reset_ops = {
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@ -216,7 +216,7 @@ static const char * const usart1_src[] = {
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"pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
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};
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const char * const usart234578_src[] = {
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static const char * const usart234578_src[] = {
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"pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
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};
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@ -224,10 +224,6 @@ static const char * const usart6_src[] = {
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"pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
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};
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static const char * const dfsdm_src[] = {
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"pclk2", "ck_mcu"
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};
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static const char * const fdcan_src[] = {
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"ck_hse", "pll3_q", "pll4_q"
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};
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@ -316,10 +312,8 @@ struct stm32_clk_mgate {
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struct clock_config {
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u32 id;
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const char *name;
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union {
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const char *parent_name;
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const char * const *parent_names;
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};
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const char *parent_name;
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const char * const *parent_names;
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int num_parents;
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unsigned long flags;
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void *cfg;
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@ -469,7 +463,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
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}
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}
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const struct clk_ops mp1_gate_clk_ops = {
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static const struct clk_ops mp1_gate_clk_ops = {
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.enable = mp1_gate_clk_enable,
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.disable = mp1_gate_clk_disable,
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.is_enabled = clk_gate_is_enabled,
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@ -585,14 +579,9 @@ clk_stm32_register_gate_ops(struct device *dev,
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spinlock_t *lock)
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{
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struct clk_init_data init = { NULL };
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struct clk_gate *gate;
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struct clk_hw *hw;
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int ret;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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@ -610,10 +599,8 @@ clk_stm32_register_gate_ops(struct device *dev,
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hw->init = &init;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(gate);
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if (ret)
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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@ -698,7 +685,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
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mp1_gate_clk_disable(hw);
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}
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const struct clk_ops mp1_mgate_clk_ops = {
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static const struct clk_ops mp1_mgate_clk_ops = {
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.enable = mp1_mgate_clk_enable,
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.disable = mp1_mgate_clk_disable,
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.is_enabled = clk_gate_is_enabled,
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@ -732,7 +719,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
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return 0;
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}
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const struct clk_ops clk_mmux_ops = {
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static const struct clk_ops clk_mmux_ops = {
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.get_parent = clk_mmux_get_parent,
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.set_parent = clk_mmux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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@ -1048,10 +1035,10 @@ struct stm32_pll_cfg {
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u32 offset;
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};
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struct clk_hw *_clk_register_pll(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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static struct clk_hw *_clk_register_pll(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
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@ -1405,7 +1392,8 @@ enum {
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G_USBH,
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G_ETHSTP,
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G_RTCAPB,
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G_TZC,
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G_TZC1,
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G_TZC2,
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G_TZPC,
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G_IWDG1,
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G_BSEC,
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@ -1417,7 +1405,7 @@ enum {
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G_LAST
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};
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struct stm32_mgate mp1_mgate[G_LAST];
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static struct stm32_mgate mp1_mgate[G_LAST];
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#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
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_mgate, _ops)\
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@ -1440,7 +1428,7 @@ struct stm32_mgate mp1_mgate[G_LAST];
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&mp1_mgate[_id], &mp1_mgate_clk_ops)
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/* Peripheral gates */
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struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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/* Multi gates */
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K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
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K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
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@ -1506,7 +1494,8 @@ struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
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K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
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K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
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K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
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K_GATE(G_TZC, RCC_APB5ENSETR, 12, 0),
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K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
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K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
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K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
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K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
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K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
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@ -1600,7 +1589,7 @@ enum {
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M_LAST
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};
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struct stm32_mmux ker_mux[M_LAST];
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static struct stm32_mmux ker_mux[M_LAST];
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#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
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[_id] = {\
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@ -1623,7 +1612,7 @@ struct stm32_mmux ker_mux[M_LAST];
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_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
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&ker_mux[_id], &clk_mmux_ops)
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const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
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static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
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/* Kernel multi mux */
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K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
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K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
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@ -1860,7 +1849,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
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PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
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CLK_IS_CRITICAL, G_RTCAPB),
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PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
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PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
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PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
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PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
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PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
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PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
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|
|
@ -1916,8 +1906,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
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KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
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KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
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KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IGNORE_UNUSED,
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G_STGEN, M_STGEN),
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KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
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KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
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KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
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KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
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|
|
@ -1948,8 +1937,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
|
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KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
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KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
|
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KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
|
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KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
|
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KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
|
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KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
|
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KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
|
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KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
|
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KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
|
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|
|
@ -1992,11 +1981,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
|
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_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
|
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|
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/* Debug clocks */
|
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FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
|
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|
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GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
|
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|
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GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
|
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GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
|
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RCC_DBGCFGR, 8, 0),
|
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|
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COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
|
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_GATE(RCC_DBGCFGR, 9, 0),
|
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|
|
|
|||
|
|
@ -219,8 +219,7 @@ static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static int s3c24xx_dclk_suspend(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
|
||||
struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
|
||||
|
||||
s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
|
||||
return 0;
|
||||
|
|
@ -228,8 +227,7 @@ static int s3c24xx_dclk_suspend(struct device *dev)
|
|||
|
||||
static int s3c24xx_dclk_resume(struct device *dev)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
|
||||
struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
|
||||
|
||||
writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -260,46 +260,45 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
|
||||
static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
|
||||
int nr_clks)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct stratix10_clock_data *clk_data;
|
||||
struct clk **clk_table;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base)) {
|
||||
pr_err("%s: failed to map clock registers\n", __func__);
|
||||
goto err;
|
||||
return ERR_CAST(base);
|
||||
}
|
||||
|
||||
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
||||
clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
goto err;
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_data->base = base;
|
||||
clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
|
||||
clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
goto err_data;
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_data->clk_data.clks = clk_table;
|
||||
clk_data->clk_data.clk_num = nr_clks;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
|
||||
return clk_data;
|
||||
|
||||
err_data:
|
||||
kfree(clk_data);
|
||||
err:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int s10_clkmgr_init(struct device_node *np)
|
||||
static int s10_clkmgr_init(struct platform_device *pdev)
|
||||
{
|
||||
struct stratix10_clock_data *clk_data;
|
||||
|
||||
clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
|
||||
if (IS_ERR(clk_data))
|
||||
return PTR_ERR(clk_data);
|
||||
|
||||
s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
|
||||
|
||||
|
|
@ -317,11 +316,7 @@ static int s10_clkmgr_init(struct device_node *np)
|
|||
|
||||
static int s10_clkmgr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
s10_clkmgr_init(np);
|
||||
|
||||
return 0;
|
||||
return s10_clkmgr_init(pdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id stratix10_clkmgr_match_table[] = {
|
||||
|
|
@ -334,6 +329,7 @@ static struct platform_driver stratix10_clkmgr_driver = {
|
|||
.probe = s10_clkmgr_probe,
|
||||
.driver = {
|
||||
.name = "stratix10-clkmgr",
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = stratix10_clkmgr_match_table,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,9 @@
|
|||
#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
|
||||
UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
|
||||
|
||||
#define UNIPHIER_LD11_SYS_CLK_HSC(idx) \
|
||||
UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
|
||||
|
||||
#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
|
||||
UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
|
||||
|
||||
|
|
@ -182,6 +185,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
|
|||
/* Index 5 reserved for eMMC PHY */
|
||||
UNIPHIER_LD11_SYS_CLK_ETHER(6),
|
||||
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
|
||||
UNIPHIER_LD11_SYS_CLK_HSC(9),
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
|
||||
UNIPHIER_LD11_SYS_CLK_AIO(40),
|
||||
UNIPHIER_LD11_SYS_CLK_EVEA(41),
|
||||
|
|
@ -215,6 +219,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
|
|||
UNIPHIER_LD20_SYS_CLK_SD,
|
||||
UNIPHIER_LD11_SYS_CLK_ETHER(6),
|
||||
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
|
||||
UNIPHIER_LD11_SYS_CLK_HSC(9),
|
||||
/* GIO is always clock-enabled: no function for 0x210c bit5 */
|
||||
/*
|
||||
* clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
|
||||
|
|
|
|||
|
|
@ -45,8 +45,9 @@
|
|||
#define ASPEED_RESET_JTAG_MASTER 3
|
||||
#define ASPEED_RESET_MIC 4
|
||||
#define ASPEED_RESET_PWM 5
|
||||
#define ASPEED_RESET_PCIVGA 6
|
||||
#define ASPEED_RESET_PECI 6
|
||||
#define ASPEED_RESET_I2C 7
|
||||
#define ASPEED_RESET_AHB 8
|
||||
#define ASPEED_RESET_CRT1 9
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@
|
|||
#define I2C6 63
|
||||
#define USART1 64
|
||||
#define RTCAPB 65
|
||||
#define TZC 66
|
||||
#define TZC1 66
|
||||
#define TZPC 67
|
||||
#define IWDG1 68
|
||||
#define BSEC 69
|
||||
|
|
@ -123,6 +123,7 @@
|
|||
#define CRC1 110
|
||||
#define USBH 111
|
||||
#define ETHSTP 112
|
||||
#define TZC2 113
|
||||
|
||||
/* Kernel clocks */
|
||||
#define SDMMC1_K 118
|
||||
|
|
@ -228,7 +229,6 @@
|
|||
#define CK_MCO2 212
|
||||
|
||||
/* TRACE & DEBUG clocks */
|
||||
#define DBG 213
|
||||
#define CK_DBG 214
|
||||
#define CK_TRACE 215
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue