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arm64: dts: qcom: Add basic devicetree support for SM8350 SoC
Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC. This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127123054.263231-6-vkoul@kernel.org [bjorn: Adjusted 4th timer interrupt, per input from Sai] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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1 changed files with 499 additions and 0 deletions
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arch/arm64/boot/dts/qcom/sm8350.dtsi
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arch/arm64/boot/dts/qcom/sm8350.dtsi
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, Linaro Limaited
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-aoss-qmp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_100>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_200>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_300>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_400>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_500>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_600>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo685";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_700>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-sm8350", "qcom,scm";
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#reset-cells = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: memory@80000000 {
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reg = <0x0 0x80000000 0x0 0x600000>;
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no-map;
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};
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xbl_aop_mem: memory@80700000 {
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no-map;
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reg = <0x0 0x80700000 0x0 0x160000>;
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};
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cmd_db: memory@80860000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x80860000 0x0 0x20000>;
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no-map;
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};
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reserved_xbl_uefi_log: memory@80880000 {
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reg = <0x0 0x80880000 0x0 0x14000>;
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no-map;
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};
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smem_mem: memory@80900000 {
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reg = <0x0 0x80900000 0x0 0x200000>;
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no-map;
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};
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cpucp_fw_mem: memory@80b00000 {
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reg = <0x0 0x80b00000 0x0 0x100000>;
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no-map;
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};
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cdsp_secure_heap: memory@80c00000 {
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reg = <0x0 0x80c00000 0x0 0x4600000>;
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no-map;
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};
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pil_camera_mem: mmeory@85200000 {
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reg = <0x0 0x85200000 0x0 0x500000>;
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no-map;
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};
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pil_video_mem: memory@85700000 {
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reg = <0x0 0x85700000 0x0 0x500000>;
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no-map;
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};
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pil_cvp_mem: memory@85c00000 {
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reg = <0x0 0x85c00000 0x0 0x500000>;
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no-map;
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};
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pil_adsp_mem: memory@86100000 {
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reg = <0x0 0x86100000 0x0 0x2100000>;
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no-map;
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};
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pil_slpi_mem: memory@88200000 {
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reg = <0x0 0x88200000 0x0 0x1500000>;
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no-map;
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};
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pil_cdsp_mem: memory@89700000 {
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reg = <0x0 0x89700000 0x0 0x1e00000>;
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no-map;
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};
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pil_ipa_fw_mem: memory@8b500000 {
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reg = <0x0 0x8b500000 0x0 0x10000>;
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no-map;
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};
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pil_ipa_gsi_mem: memory@8b510000 {
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reg = <0x0 0x8b510000 0x0 0xa000>;
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no-map;
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};
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pil_gpu_mem: memory@8b51a000 {
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reg = <0x0 0x8b51a000 0x0 0x2000>;
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no-map;
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};
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pil_spss_mem: memory@8b600000 {
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reg = <0x0 0x8b600000 0x0 0x100000>;
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no-map;
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};
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pil_modem_mem: memory@8b800000 {
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reg = <0x0 0x8b800000 0x0 0x10000000>;
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no-map;
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};
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hyp_reserved_mem: memory@d0000000 {
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reg = <0x0 0xd0000000 0x0 0x800000>;
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no-map;
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};
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pil_trustedvm_mem: memory@d0800000 {
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reg = <0x0 0xd0800000 0x0 0x76f7000>;
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no-map;
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};
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qrtr_shbuf: memory@d7ef7000 {
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reg = <0x0 0xd7ef7000 0x0 0x9000>;
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no-map;
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};
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chan0_shbuf: memory@d7f00000 {
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reg = <0x0 0xd7f00000 0x0 0x80000>;
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no-map;
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};
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chan1_shbuf: memory@d7f80000 {
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reg = <0x0 0xd7f80000 0x0 0x80000>;
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no-map;
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};
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removed_mem: memory@d8800000 {
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reg = <0x0 0xd8800000 0x0 0x6800000>;
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no-map;
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};
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sm8350";
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reg = <0x0 0x00100000 0x0 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo", "sleep_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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};
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ipcc: mailbox@408000 {
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compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
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reg = <0 0x00408000 0 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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qupv3_id_1: geniqup@9c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x009c0000 0x0 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc 121>,
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<&gcc 122>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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uart2: serial@98c000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0 0x0098c000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc 83>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_uart3_default_state>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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#hwlock-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8350-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
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qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
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<59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
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<69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
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<156 716 12>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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aoss_qmp: qmp@c300000 {
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compatible = "qcom,sm8350-aoss-qmp";
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reg = <0 0x0c300000 0 0x100000>;
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interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
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#clock-cells = <0>;
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#power-domain-cells = <1>;
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};
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sm8350-tlmm";
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reg = <0 0x0f100000 0 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 203>;
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qup_uart3_default_state: qup-uart3-default-state {
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rx {
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pins = "gpio18";
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function = "qup3";
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};
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tx {
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pins = "gpio19";
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function = "qup3";
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};
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};
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
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<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer@17c20000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x17c20000 0x0 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c21000 0x0 0x1000>,
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<0x0 0x17c22000 0x0 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c23000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c25000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c27000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c29000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c2b000 0x0 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x17c2d000 0x0 0x1000>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x0 0x18200000 0x0 0x10000>,
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<0x0 0x18210000 0x0 0x10000>,
|
||||
<0x0 0x18220000 0x0 0x10000>;
|
||||
reg-names = "drv-0", "drv-1", "drv-2";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,tcs-offset = <0xd00>;
|
||||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>, <CONTROL_TCS 1>;
|
||||
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sm8350-rpmh-clk";
|
||||
#clock-cells = <1>;
|
||||
clock-names = "xo";
|
||||
clocks = <&xo_board>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
Loading…
Reference in a new issue