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drm/amdgpu/display: use blanked rather than plane state for sync groups

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We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation.  Check both to determine
the proper blanked state.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
Fixes: 5fc0cbfad4 ("drm/amd/display: determine if a pipe is synced by plane state")
Cc: nicholas.kazlauskas@amd.com
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Alex Deucher 2020-06-02 17:22:48 -04:00
parent 14ed1c908a
commit b7f839d292
1 changed files with 20 additions and 4 deletions
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24
drivers/gpu/drm/amd/display/dc/core/dc.c
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@ -1016,9 +1016,17 @@ static void program_timing_sync(
}
}
/* set first pipe with plane as master */
/* set first unblanked pipe as master */
for (j = 0; j < group_size; j++) {
if (pipe_set[j]->plane_state) {
bool is_blanked;
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
is_blanked =
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
else
is_blanked =
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
if (!is_blanked) {
if (j == 0)
break;
@ -1039,9 +1047,17 @@ static void program_timing_sync(
status->timing_sync_info.master = false;
}
/* remove any other pipes with plane as they have already been synced */
/* remove any other unblanked pipes as they have already been synced */
for (j = j + 1; j < group_size; j++) {
if (pipe_set[j]->plane_state) {
bool is_blanked;
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
is_blanked =
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
else
is_blanked =
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
if (!is_blanked) {
group_size--;
pipe_set[j] = pipe_set[group_size];
j--;