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[MIPS] Fix 64-bit IP checksum code
Use unsigned loads to avoid possible misscalculation of IP checksums. This
bug was instruced in f761106cd728bcf65b7fe161b10221ee00cf7132 (lmo) /
ed99e2bc1d
(kernel.org).
[Original fix by Atsushi. Improved instruction scheduling and fix for
unaligned unsigned load by me -- Ralf]
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
9824b8f113
commit
b80a1b8081
1 changed files with 17 additions and 4 deletions
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@ -39,12 +39,14 @@
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#ifdef USE_DOUBLE
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#define LOAD ld
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#define LOAD32 lwu
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#define ADD daddu
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#define NBYTES 8
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#else
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#define LOAD lw
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#define LOAD32 lw
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#define ADD addu
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#define NBYTES 4
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@ -60,6 +62,14 @@
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ADD sum, v1; \
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.set pop
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#define ADDC32(sum,reg) \
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.set push; \
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.set noat; \
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addu sum, reg; \
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sltu v1, sum, reg; \
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addu sum, v1; \
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.set pop
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#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
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LOAD _t0, (offset + UNIT(0))(src); \
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LOAD _t1, (offset + UNIT(1))(src); \
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@ -132,7 +142,7 @@ LEAF(csum_partial)
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beqz t8, .Lqword_align
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andi t8, src, 0x8
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lw t0, 0x00(src)
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LOAD32 t0, 0x00(src)
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LONG_SUBU a1, a1, 0x4
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ADDC(sum, t0)
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PTR_ADDU src, src, 0x4
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@ -211,7 +221,7 @@ LEAF(csum_partial)
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LONG_SRL t8, t8, 0x2
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.Lend_words:
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lw t0, (src)
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LOAD32 t0, (src)
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LONG_SUBU t8, t8, 0x1
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ADDC(sum, t0)
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.set reorder /* DADDI_WAR */
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@ -230,6 +240,9 @@ LEAF(csum_partial)
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/* Still a full word to go */
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ulw t1, (src)
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PTR_ADDIU src, 4
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#ifdef USE_DOUBLE
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dsll t1, t1, 32 /* clear lower 32bit */
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#endif
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ADDC(sum, t1)
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1: move t1, zero
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@ -280,7 +293,7 @@ LEAF(csum_partial)
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1:
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.set reorder
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/* Add the passed partial csum. */
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ADDC(sum, a2)
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ADDC32(sum, a2)
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jr ra
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.set noreorder
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END(csum_partial)
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@ -681,7 +694,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
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.set pop
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1:
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.set reorder
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ADDC(sum, psum)
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ADDC32(sum, psum)
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jr ra
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.set noreorder
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