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x86: Add new MSRs and MSR bits used for Intel Skylake PMU support
Add new MSRs (LBR_INFO) and some new MSR bits used by the Intel Skylake PMU driver. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-4-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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2 changed files with 13 additions and 0 deletions
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@ -73,6 +73,12 @@
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#define MSR_LBR_CORE_FROM 0x00000040
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#define MSR_LBR_CORE_TO 0x00000060
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#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
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#define LBR_INFO_MISPRED BIT_ULL(63)
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#define LBR_INFO_IN_TX BIT_ULL(62)
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#define LBR_INFO_ABORT BIT_ULL(61)
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#define LBR_INFO_CYCLES 0xffff
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#define MSR_IA32_PEBS_ENABLE 0x000003f1
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#define MSR_IA32_DS_AREA 0x00000600
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345
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@ -159,6 +159,13 @@ struct x86_pmu_capability {
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*/
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#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
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#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
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#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
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#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
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#define GLOBAL_STATUS_ASIF BIT_ULL(60)
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#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
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#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
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/*
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* IBS cpuid feature detection
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*/
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