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drm/amdgpu: update one PDE at a time v2
Horrible inefficient, but avoids problems when the root PD size becomes to big. v2: remove incr as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 36 additions and 48 deletions
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@ -1069,18 +1069,20 @@ static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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* Makes sure all entries in @parent are up to date.
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* Returns 0 for success, error for failure.
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*/
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static int amdgpu_vm_update_level(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_vm_pt *parent)
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static int amdgpu_vm_update_pde(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_vm_pt *parent,
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struct amdgpu_vm_pt *entry)
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{
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struct amdgpu_pte_update_params params;
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struct amdgpu_bo *bo = entry->base.bo;
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struct amdgpu_bo *shadow;
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struct amdgpu_ring *ring = NULL;
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uint64_t pd_addr, shadow_addr = 0;
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unsigned pt_idx, ndw = 0;
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struct amdgpu_job *job;
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struct amdgpu_pte_update_params params;
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struct dma_fence *fence = NULL;
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uint32_t incr;
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unsigned ndw = 0;
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uint64_t pde, pt;
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int r;
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@ -1102,20 +1104,14 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
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ring = container_of(vm->entity.sched, struct amdgpu_ring,
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sched);
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/* padding, etc. */
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/* should be sufficient for two commands plus padding, etc. */
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ndw = 64;
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/* assume the worst case */
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ndw += parent->last_entry_used * 6;
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pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
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if (shadow) {
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if (shadow)
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shadow_addr = amdgpu_bo_gpu_offset(shadow);
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ndw *= 2;
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} else {
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else
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shadow_addr = 0;
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}
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r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
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if (r)
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@ -1125,40 +1121,30 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev,
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params.func = amdgpu_vm_do_set_ptes;
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}
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spin_lock(&vm->status_lock);
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list_del_init(&entry->base.vm_status);
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spin_unlock(&vm->status_lock);
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/* walk over the address space and update the directory */
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for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
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struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
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struct amdgpu_bo *bo = entry->base.bo;
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uint64_t pde, pt;
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if (bo == NULL)
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continue;
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spin_lock(&vm->status_lock);
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list_del_init(&entry->base.vm_status);
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spin_unlock(&vm->status_lock);
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pt = amdgpu_bo_gpu_offset(bo);
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pt = amdgpu_gart_get_vm_pde(adev, pt);
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/* Don't update huge pages here */
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if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) ||
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parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID))
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continue;
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parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID;
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incr = amdgpu_bo_size(bo);
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if (shadow) {
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pde = shadow_addr + pt_idx * 8;
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params.func(¶ms, pde, pt, 1, incr,
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AMDGPU_PTE_VALID);
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}
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pde = pd_addr + pt_idx * 8;
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params.func(¶ms, pde, pt, 1, incr, AMDGPU_PTE_VALID);
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pt = amdgpu_bo_gpu_offset(bo);
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pt = amdgpu_gart_get_vm_pde(adev, pt);
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/* Don't update huge pages here */
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if (entry->addr & AMDGPU_PDE_PTE ||
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entry->addr == (pt | AMDGPU_PTE_VALID)) {
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if (!vm->use_cpu_for_update)
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amdgpu_job_free(job);
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return 0;
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}
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entry->addr = pt | AMDGPU_PTE_VALID;
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if (shadow) {
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pde = shadow_addr + (entry - parent->entries) * 8;
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params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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}
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pde = pd_addr + (entry - parent->entries) * 8;
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params.func(¶ms, pde, pt, 1, 0, AMDGPU_PTE_VALID);
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if (!vm->use_cpu_for_update) {
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if (params.ib->length_dw == 0) {
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amdgpu_job_free(job);
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@ -1249,14 +1235,16 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
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bo = bo_base->bo->parent;
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if (bo) {
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struct amdgpu_vm_bo_base *parent;
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struct amdgpu_vm_pt *pt;
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struct amdgpu_vm_pt *pt, *entry;
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parent = list_first_entry(&bo->va,
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struct amdgpu_vm_bo_base,
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bo_list);
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pt = container_of(parent, struct amdgpu_vm_pt, base);
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entry = container_of(bo_base, struct amdgpu_vm_pt,
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base);
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r = amdgpu_vm_update_level(adev, vm, pt);
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r = amdgpu_vm_update_pde(adev, vm, pt, entry);
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if (r) {
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amdgpu_vm_invalidate_level(vm, &vm->root);
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return r;
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