mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
Merge tag 'vmwgfx-next-4.19-3' of git://people.freedesktop.org/~thomash/linux into drm-next
This introduces a header update and support for multisample surfaces. Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/d020efb8-776d-5e8f-9d9f-122591e074d6@vmware.com
This commit is contained in:
commit
b861686b18
16 changed files with 2083 additions and 1020 deletions
|
@ -47,10 +47,10 @@
|
||||||
* the SVGA3D protocol and remain reserved; they should not be used in the
|
* the SVGA3D protocol and remain reserved; they should not be used in the
|
||||||
* future.
|
* future.
|
||||||
*
|
*
|
||||||
* IDs between 1040 and 1999 (inclusive) are available for use by the
|
* IDs between 1040 and 2999 (inclusive) are available for use by the
|
||||||
* current SVGA3D protocol.
|
* current SVGA3D protocol.
|
||||||
*
|
*
|
||||||
* FIFO clients other than SVGA3D should stay below 1000, or at 2000
|
* FIFO clients other than SVGA3D should stay below 1000, or at 3000
|
||||||
* and up.
|
* and up.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
@ -90,19 +90,19 @@ typedef enum {
|
||||||
SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
|
SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
|
||||||
SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
|
SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
|
||||||
SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
|
SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
|
||||||
SVGA_3D_CMD_VIDEO_CREATE_DECODER = 1072,
|
SVGA_3D_CMD_DEAD4 = 1072,
|
||||||
SVGA_3D_CMD_VIDEO_DESTROY_DECODER = 1073,
|
SVGA_3D_CMD_DEAD5 = 1073,
|
||||||
SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR = 1074,
|
SVGA_3D_CMD_DEAD6 = 1074,
|
||||||
SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR = 1075,
|
SVGA_3D_CMD_DEAD7 = 1075,
|
||||||
SVGA_3D_CMD_VIDEO_DECODE_START_FRAME = 1076,
|
SVGA_3D_CMD_DEAD8 = 1076,
|
||||||
SVGA_3D_CMD_VIDEO_DECODE_RENDER = 1077,
|
SVGA_3D_CMD_DEAD9 = 1077,
|
||||||
SVGA_3D_CMD_VIDEO_DECODE_END_FRAME = 1078,
|
SVGA_3D_CMD_DEAD10 = 1078,
|
||||||
SVGA_3D_CMD_VIDEO_PROCESS_FRAME = 1079,
|
SVGA_3D_CMD_DEAD11 = 1079,
|
||||||
SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
|
SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
|
||||||
SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
|
SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
|
||||||
SVGA_3D_CMD_SCREEN_DMA = 1082,
|
SVGA_3D_CMD_SCREEN_DMA = 1082,
|
||||||
SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE = 1083,
|
SVGA_3D_CMD_DEAD1 = 1083,
|
||||||
SVGA_3D_CMD_OPEN_CONTEXT_SURFACE = 1084,
|
SVGA_3D_CMD_DEAD2 = 1084,
|
||||||
|
|
||||||
SVGA_3D_CMD_LOGICOPS_BITBLT = 1085,
|
SVGA_3D_CMD_LOGICOPS_BITBLT = 1085,
|
||||||
SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1086,
|
SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1086,
|
||||||
|
@ -218,7 +218,7 @@ typedef enum {
|
||||||
SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
|
SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
|
||||||
SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
|
SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
|
||||||
SVGA_3D_CMD_DX_PRED_COPY = 1179,
|
SVGA_3D_CMD_DX_PRED_COPY = 1179,
|
||||||
SVGA_3D_CMD_DX_STRETCHBLT = 1180,
|
SVGA_3D_CMD_DX_PRESENTBLT = 1180,
|
||||||
SVGA_3D_CMD_DX_GENMIPS = 1181,
|
SVGA_3D_CMD_DX_GENMIPS = 1181,
|
||||||
SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
|
SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
|
||||||
SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
|
SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
|
||||||
|
@ -255,7 +255,7 @@ typedef enum {
|
||||||
SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
|
SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
|
||||||
SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
|
SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
|
||||||
SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
|
SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
|
||||||
SVGA_3D_CMD_DX_BIND_SHADER_ON_CONTEXT = 1217,
|
SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217,
|
||||||
SVGA_3D_CMD_DX_HINT = 1218,
|
SVGA_3D_CMD_DX_HINT = 1218,
|
||||||
SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
|
SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
|
||||||
SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
|
SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
|
||||||
|
@ -263,17 +263,47 @@ typedef enum {
|
||||||
SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
|
SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reserve some IDs to be used for the DX11 shader types.
|
* Reserve some IDs to be used for the SM5 shader types.
|
||||||
*/
|
*/
|
||||||
SVGA_3D_CMD_DX_RESERVED1 = 1223,
|
SVGA_3D_CMD_DX_RESERVED1 = 1223,
|
||||||
SVGA_3D_CMD_DX_RESERVED2 = 1224,
|
SVGA_3D_CMD_DX_RESERVED2 = 1224,
|
||||||
SVGA_3D_CMD_DX_RESERVED3 = 1225,
|
SVGA_3D_CMD_DX_RESERVED3 = 1225,
|
||||||
|
|
||||||
SVGA_3D_CMD_DX_MAX = 1226,
|
SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
|
||||||
SVGA_3D_CMD_MAX = 1226,
|
SVGA_3D_CMD_DX_MAX = 1227,
|
||||||
|
|
||||||
|
SVGA_3D_CMD_SCREEN_COPY = 1227,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reserve some IDs to be used for video.
|
||||||
|
*/
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED1 = 1228,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED2 = 1229,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED3 = 1230,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED4 = 1231,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED5 = 1232,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED6 = 1233,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED7 = 1234,
|
||||||
|
SVGA_3D_CMD_VIDEO_RESERVED8 = 1235,
|
||||||
|
|
||||||
|
SVGA_3D_CMD_GROW_OTABLE = 1236,
|
||||||
|
SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
|
||||||
|
SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238,
|
||||||
|
|
||||||
|
SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239,
|
||||||
|
|
||||||
|
SVGA_3D_CMD_DX_RESOLVE_COPY = 1240,
|
||||||
|
SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241,
|
||||||
|
SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242,
|
||||||
|
SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
|
||||||
|
SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
|
||||||
|
|
||||||
|
SVGA_3D_CMD_MAX = 1245,
|
||||||
SVGA_3D_CMD_FUTURE_MAX = 3000
|
SVGA_3D_CMD_FUTURE_MAX = 3000
|
||||||
} SVGAFifo3dCmdId;
|
} SVGAFifo3dCmdId;
|
||||||
|
|
||||||
|
#define SVGA_NUM_3D_CMD (SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* FIFO command format definitions:
|
* FIFO command format definitions:
|
||||||
*/
|
*/
|
||||||
|
@ -302,7 +332,7 @@ typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
uint32 sid;
|
uint32 sid;
|
||||||
SVGA3dSurfaceFlags surfaceFlags;
|
SVGA3dSurface1Flags surfaceFlags;
|
||||||
SVGA3dSurfaceFormat format;
|
SVGA3dSurfaceFormat format;
|
||||||
/*
|
/*
|
||||||
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
|
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
|
||||||
|
@ -328,7 +358,7 @@ typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
uint32 sid;
|
uint32 sid;
|
||||||
SVGA3dSurfaceFlags surfaceFlags;
|
SVGA3dSurface1Flags surfaceFlags;
|
||||||
SVGA3dSurfaceFormat format;
|
SVGA3dSurfaceFormat format;
|
||||||
/*
|
/*
|
||||||
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
|
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
|
||||||
|
@ -460,6 +490,28 @@ struct {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
|
SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Perform a surface copy within the same image.
|
||||||
|
* The src/dest boxes are allowed to overlap.
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
SVGA3dSurfaceImageId surface;
|
||||||
|
SVGA3dCopyBox box;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdIntraSurfaceCopy; /* SVGA_3D_CMD_INTRA_SURFACE_COPY */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
uint32 srcSid;
|
||||||
|
uint32 destSid;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
|
@ -773,6 +825,17 @@ struct {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dVertexElement;
|
SVGA3dVertexElement;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Should the vertex element respect the stream value? The high bit of the
|
||||||
|
* stream should be set to indicate that the stream should be respected. If
|
||||||
|
* the high bit is not set, the stream will be ignored and replaced by the index
|
||||||
|
* of the position of the currently considered vertex element.
|
||||||
|
*
|
||||||
|
* All guests should set this bit and correctly specify the stream going
|
||||||
|
* forward.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_VERTEX_ELEMENT_RESPECT_STREAM (1 << 7)
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
|
@ -1103,8 +1166,6 @@ struct {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
|
SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
|
@ -1147,38 +1208,6 @@ struct SVGA3dCmdScreenDMA {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
|
SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
|
||||||
|
|
||||||
/*
|
|
||||||
* Set Unity Surface Cookie
|
|
||||||
*
|
|
||||||
* Associates the supplied cookie with the surface id for use with
|
|
||||||
* Unity. This cookie is a hint from guest to host, there is no way
|
|
||||||
* for the guest to readback the cookie and the host is free to drop
|
|
||||||
* the cookie association at will. The default value for the cookie
|
|
||||||
* on all surfaces is 0.
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef
|
|
||||||
#include "vmware_pack_begin.h"
|
|
||||||
struct SVGA3dCmdSetUnitySurfaceCookie {
|
|
||||||
uint32 sid;
|
|
||||||
uint64 cookie;
|
|
||||||
}
|
|
||||||
#include "vmware_pack_end.h"
|
|
||||||
SVGA3dCmdSetUnitySurfaceCookie; /* SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Open a context-specific surface in a non-context-specific manner.
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef
|
|
||||||
#include "vmware_pack_begin.h"
|
|
||||||
struct SVGA3dCmdOpenContextSurface {
|
|
||||||
uint32 sid;
|
|
||||||
}
|
|
||||||
#include "vmware_pack_end.h"
|
|
||||||
SVGA3dCmdOpenContextSurface; /* SVGA_3D_CMD_OPEN_CONTEXT_SURFACE */
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Logic ops
|
* Logic ops
|
||||||
*/
|
*/
|
||||||
|
@ -1325,7 +1354,7 @@ typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
SVGA3dSurfaceFormat format;
|
SVGA3dSurfaceFormat format;
|
||||||
SVGA3dSurfaceFlags surfaceFlags;
|
SVGA3dSurface1Flags surface1Flags;
|
||||||
uint32 numMipLevels;
|
uint32 numMipLevels;
|
||||||
uint32 multisampleCount;
|
uint32 multisampleCount;
|
||||||
SVGA3dTextureFilter autogenFilter;
|
SVGA3dTextureFilter autogenFilter;
|
||||||
|
@ -1333,7 +1362,11 @@ struct {
|
||||||
SVGAMobId mobid;
|
SVGAMobId mobid;
|
||||||
uint32 arraySize;
|
uint32 arraySize;
|
||||||
uint32 mobPitch;
|
uint32 mobPitch;
|
||||||
uint32 pad[5];
|
SVGA3dSurface2Flags surface2Flags;
|
||||||
|
uint8 multisamplePattern;
|
||||||
|
uint8 qualityLevel;
|
||||||
|
uint8 pad0[2];
|
||||||
|
uint32 pad1[3];
|
||||||
}
|
}
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGAOTableSurfaceEntry;
|
SVGAOTableSurfaceEntry;
|
||||||
|
@ -1361,7 +1394,8 @@ struct {
|
||||||
SVGAOTableShaderEntry;
|
SVGAOTableShaderEntry;
|
||||||
#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
|
#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
|
||||||
|
|
||||||
#define SVGA_STFLAG_PRIMARY (1 << 0)
|
#define SVGA_STFLAG_PRIMARY (1 << 0)
|
||||||
|
#define SVGA_STFLAG_RESERVED (1 << 1) /* Added with cap SVGA_CAP_HP_CMD_QUEUE */
|
||||||
typedef uint32 SVGAScreenTargetFlags;
|
typedef uint32 SVGAScreenTargetFlags;
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
|
@ -1529,6 +1563,25 @@ struct {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
|
SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Guests using SVGA_3D_CMD_GROW_OTABLE are promising that
|
||||||
|
* the new OTable contains the same contents as the old one, except possibly
|
||||||
|
* for some new invalid entries at the end.
|
||||||
|
*
|
||||||
|
* (Otherwise, guests should use one of the SetOTableBase commands.)
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
SVGAOTableType type;
|
||||||
|
PPN64 baseAddress;
|
||||||
|
uint32 sizeInBytes;
|
||||||
|
uint32 validSizeInBytes;
|
||||||
|
SVGAMobFormat ptDepth;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdGrowOTable; /* SVGA_3D_CMD_GROW_OTABLE */
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
|
@ -1616,7 +1669,7 @@ typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDefineGBSurface {
|
struct SVGA3dCmdDefineGBSurface {
|
||||||
uint32 sid;
|
uint32 sid;
|
||||||
SVGA3dSurfaceFlags surfaceFlags;
|
SVGA3dSurface1Flags surfaceFlags;
|
||||||
SVGA3dSurfaceFormat format;
|
SVGA3dSurfaceFormat format;
|
||||||
uint32 numMipLevels;
|
uint32 numMipLevels;
|
||||||
uint32 multisampleCount;
|
uint32 multisampleCount;
|
||||||
|
@ -1626,6 +1679,45 @@ struct SVGA3dCmdDefineGBSurface {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
|
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Defines a guest-backed surface, adding the arraySize field.
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDefineGBSurface_v2 {
|
||||||
|
uint32 sid;
|
||||||
|
SVGA3dSurface1Flags surfaceFlags;
|
||||||
|
SVGA3dSurfaceFormat format;
|
||||||
|
uint32 numMipLevels;
|
||||||
|
uint32 multisampleCount;
|
||||||
|
SVGA3dTextureFilter autogenFilter;
|
||||||
|
SVGA3dSize size;
|
||||||
|
uint32 arraySize;
|
||||||
|
uint32 pad;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Defines a guest-backed surface, adding the larger flags.
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDefineGBSurface_v3 {
|
||||||
|
uint32 sid;
|
||||||
|
SVGA3dSurfaceAllFlags surfaceFlags;
|
||||||
|
SVGA3dSurfaceFormat format;
|
||||||
|
uint32 numMipLevels;
|
||||||
|
uint32 multisampleCount;
|
||||||
|
SVGA3dMSPattern multisamplePattern;
|
||||||
|
SVGA3dMSQualityLevel qualityLevel;
|
||||||
|
SVGA3dTextureFilter autogenFilter;
|
||||||
|
SVGA3dSize size;
|
||||||
|
uint32 arraySize;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Destroy a guest-backed surface.
|
* Destroy a guest-backed surface.
|
||||||
*/
|
*/
|
||||||
|
@ -1673,7 +1765,7 @@ SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct{
|
struct SVGA3dCmdCondBindGBSurface {
|
||||||
uint32 sid;
|
uint32 sid;
|
||||||
SVGAMobId testMobid;
|
SVGAMobId testMobid;
|
||||||
SVGAMobId mobid;
|
SVGAMobId mobid;
|
||||||
|
@ -2067,6 +2159,26 @@ struct {
|
||||||
uint32 mobOffset;
|
uint32 mobOffset;
|
||||||
}
|
}
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE*/
|
SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
uint32 stid;
|
||||||
|
SVGA3dSurfaceImageId dest;
|
||||||
|
|
||||||
|
uint32 statusMobId;
|
||||||
|
uint32 statusMobOffset;
|
||||||
|
|
||||||
|
/* Reserved fields */
|
||||||
|
uint32 mustBeInvalidId;
|
||||||
|
uint32 mustBeZero;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */
|
||||||
|
|
||||||
|
#define SVGA_SCREEN_COPY_STATUS_FAILURE 0x00
|
||||||
|
#define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01
|
||||||
|
#define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF
|
||||||
|
|
||||||
#endif /* _SVGA3D_CMD_H_ */
|
#endif /* _SVGA3D_CMD_H_ */
|
||||||
|
|
|
@ -230,9 +230,9 @@ typedef enum {
|
||||||
SVGA3D_DEVCAP_DEAD2 = 94,
|
SVGA3D_DEVCAP_DEAD2 = 94,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Does the device support the DX commands?
|
* Does the device support DXContexts?
|
||||||
*/
|
*/
|
||||||
SVGA3D_DEVCAP_DX = 95,
|
SVGA3D_DEVCAP_DXCONTEXT = 95,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* What is the maximum size of a texture array?
|
* What is the maximum size of a texture array?
|
||||||
|
@ -242,21 +242,47 @@ typedef enum {
|
||||||
SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96,
|
SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* What is the maximum number of vertex buffers that can
|
* What is the maximum number of vertex buffers or vertex input registers
|
||||||
* be used in the DXContext inputAssembly?
|
* that can be expected to work correctly with a DXContext?
|
||||||
|
*
|
||||||
|
* The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
|
||||||
|
* anything in excess of this cap is not guaranteed to render correctly.
|
||||||
|
*
|
||||||
|
* Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
|
||||||
|
* input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
|
||||||
|
* SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
|
||||||
|
* but only the registers up to this cap value are guaranteed to render
|
||||||
|
* correctly.
|
||||||
|
*
|
||||||
|
* If guest-drivers are able to expose a lower-limit, it's recommended
|
||||||
|
* that they clamp to this value. Otherwise, the host will make a
|
||||||
|
* best-effort on case-by-case basis if guests exceed this.
|
||||||
*/
|
*/
|
||||||
SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97,
|
SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* What is the maximum number of constant buffers
|
* What is the maximum number of constant buffers that can be expected to
|
||||||
* that can be expected to work correctly with a
|
* work correctly with a DX context?
|
||||||
* DX context?
|
*
|
||||||
|
* The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
|
||||||
|
* anything in excess of this cap is not guaranteed to render correctly.
|
||||||
|
*
|
||||||
|
* If guest-drivers are able to expose a lower-limit, it's recommended
|
||||||
|
* that they clamp to this value. Otherwise, the host will make a
|
||||||
|
* best-effort on case-by-case basis if guests exceed this.
|
||||||
*/
|
*/
|
||||||
SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98,
|
SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Does the device support provoking vertex control?
|
* Does the device support provoking vertex control?
|
||||||
* If zero, the first vertex will always be the provoking vertex.
|
*
|
||||||
|
* If this cap is present, the provokingVertexLast field in the
|
||||||
|
* rasterizer state is enabled. (Guests can then set it to FALSE,
|
||||||
|
* meaning that the first vertex is the provoking vertex, or TRUE,
|
||||||
|
* meaning that the last verteix is the provoking vertex.)
|
||||||
|
*
|
||||||
|
* If this cap is FALSE, then guests should set the provokingVertexLast
|
||||||
|
* to FALSE, otherwise rendering behavior is undefined.
|
||||||
*/
|
*/
|
||||||
SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99,
|
SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99,
|
||||||
|
|
||||||
|
@ -282,7 +308,7 @@ typedef enum {
|
||||||
SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119,
|
SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119,
|
||||||
SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120,
|
SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120,
|
||||||
SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121,
|
SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121,
|
||||||
SVGA3D_DEVCAP_DXFMT_BUMPL8V8U8 = 122,
|
SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 = 122,
|
||||||
SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123,
|
SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123,
|
||||||
SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124,
|
SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124,
|
||||||
SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125,
|
SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125,
|
||||||
|
@ -321,8 +347,8 @@ typedef enum {
|
||||||
SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158,
|
SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158,
|
||||||
SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159,
|
SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159,
|
||||||
SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160,
|
SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160,
|
||||||
SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS = 161,
|
SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 = 161,
|
||||||
SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT = 162,
|
SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT = 162,
|
||||||
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163,
|
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163,
|
||||||
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164,
|
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164,
|
||||||
SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165,
|
SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165,
|
||||||
|
@ -340,8 +366,8 @@ typedef enum {
|
||||||
SVGA3D_DEVCAP_DXFMT_R32_SINT = 177,
|
SVGA3D_DEVCAP_DXFMT_R32_SINT = 177,
|
||||||
SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178,
|
SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178,
|
||||||
SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179,
|
SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179,
|
||||||
SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS = 180,
|
SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 = 180,
|
||||||
SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT = 181,
|
SVGA3D_DEVCAP_DXFMT_X24_G8_UINT = 181,
|
||||||
SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182,
|
SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182,
|
||||||
SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183,
|
SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183,
|
||||||
SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184,
|
SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184,
|
||||||
|
@ -405,6 +431,17 @@ typedef enum {
|
||||||
SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
|
SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
|
||||||
SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
|
SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Advertises shaderModel 4.1 support, independent blend-states,
|
||||||
|
* cube-map arrays, and a higher vertex input registers limit.
|
||||||
|
*
|
||||||
|
* (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.)
|
||||||
|
*/
|
||||||
|
SVGA3D_DEVCAP_SM41 = 244,
|
||||||
|
|
||||||
|
SVGA3D_DEVCAP_MULTISAMPLE_2X = 245,
|
||||||
|
SVGA3D_DEVCAP_MULTISAMPLE_4X = 246,
|
||||||
|
|
||||||
SVGA3D_DEVCAP_MAX /* This must be the last index. */
|
SVGA3D_DEVCAP_MAX /* This must be the last index. */
|
||||||
} SVGA3dDevCapIndex;
|
} SVGA3dDevCapIndex;
|
||||||
|
|
||||||
|
@ -420,9 +457,7 @@ typedef enum {
|
||||||
* MIPS: Does the format support mip levels?
|
* MIPS: Does the format support mip levels?
|
||||||
* ARRAY: Does the format support texture arrays?
|
* ARRAY: Does the format support texture arrays?
|
||||||
* VOLUME: Does the format support having volume?
|
* VOLUME: Does the format support having volume?
|
||||||
* MULTISAMPLE_2: Does the format support 2x multisample?
|
* MULTISAMPLE: Does the format support multisample?
|
||||||
* MULTISAMPLE_4: Does the format support 4x multisample?
|
|
||||||
* MULTISAMPLE_8: Does the format support 8x multisample?
|
|
||||||
*/
|
*/
|
||||||
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
|
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
|
||||||
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
|
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
|
||||||
|
@ -433,20 +468,8 @@ typedef enum {
|
||||||
#define SVGA3D_DXFMT_ARRAY (1 << 6)
|
#define SVGA3D_DXFMT_ARRAY (1 << 6)
|
||||||
#define SVGA3D_DXFMT_VOLUME (1 << 7)
|
#define SVGA3D_DXFMT_VOLUME (1 << 7)
|
||||||
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
|
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
|
||||||
#define SVGADX_DXFMT_MULTISAMPLE_2 (1 << 9)
|
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
|
||||||
#define SVGADX_DXFMT_MULTISAMPLE_4 (1 << 10)
|
#define SVGA3D_DXFMT_MAX (1 << 10)
|
||||||
#define SVGADX_DXFMT_MULTISAMPLE_8 (1 << 11)
|
|
||||||
#define SVGADX_DXFMT_MAX (1 << 12)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Convenience mask for any multisample capability.
|
|
||||||
*
|
|
||||||
* The multisample bits imply both load and render capability.
|
|
||||||
*/
|
|
||||||
#define SVGA3D_DXFMT_MULTISAMPLE ( \
|
|
||||||
SVGADX_DXFMT_MULTISAMPLE_2 | \
|
|
||||||
SVGADX_DXFMT_MULTISAMPLE_4 | \
|
|
||||||
SVGADX_DXFMT_MULTISAMPLE_8 )
|
|
||||||
|
|
||||||
typedef union {
|
typedef union {
|
||||||
Bool b;
|
Bool b;
|
||||||
|
|
|
@ -57,6 +57,16 @@ typedef uint32 SVGA3dInputClassification;
|
||||||
#define SVGA3D_RESOURCE_TYPE_MAX 7
|
#define SVGA3D_RESOURCE_TYPE_MAX 7
|
||||||
typedef uint32 SVGA3dResourceType;
|
typedef uint32 SVGA3dResourceType;
|
||||||
|
|
||||||
|
#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0)
|
||||||
|
#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1)
|
||||||
|
#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2)
|
||||||
|
#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3)
|
||||||
|
#define SVGA3D_COLOR_WRITE_ENABLE_ALL (SVGA3D_COLOR_WRITE_ENABLE_RED | \
|
||||||
|
SVGA3D_COLOR_WRITE_ENABLE_GREEN | \
|
||||||
|
SVGA3D_COLOR_WRITE_ENABLE_BLUE | \
|
||||||
|
SVGA3D_COLOR_WRITE_ENABLE_ALPHA)
|
||||||
|
typedef uint8 SVGA3dColorWriteEnable;
|
||||||
|
|
||||||
#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
|
#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
|
||||||
#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
|
#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
|
||||||
typedef uint8 SVGA3dDepthWriteMask;
|
typedef uint8 SVGA3dDepthWriteMask;
|
||||||
|
@ -89,17 +99,28 @@ typedef uint8 SVGA3dCullMode;
|
||||||
#define SVGA3D_COMPARISON_MAX 9
|
#define SVGA3D_COMPARISON_MAX 9
|
||||||
typedef uint8 SVGA3dComparisonFunc;
|
typedef uint8 SVGA3dComparisonFunc;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SVGA3D_MULTISAMPLE_RAST_DISABLE disables MSAA for all primitives.
|
||||||
|
* SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE, which is supported in SM41,
|
||||||
|
* disables MSAA for lines only.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0
|
||||||
|
#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1
|
||||||
|
#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1
|
||||||
|
#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2
|
||||||
|
#define SVGA3D_MULTISAMPLE_RAST_MAX 2
|
||||||
|
typedef uint8 SVGA3dMultisampleRastEnable;
|
||||||
|
|
||||||
#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
|
#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
|
||||||
|
#define SVGA3D_DX_MAX_VERTEXINPUTREGISTERS 16
|
||||||
|
#define SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS 32
|
||||||
#define SVGA3D_DX_MAX_SOTARGETS 4
|
#define SVGA3D_DX_MAX_SOTARGETS 4
|
||||||
#define SVGA3D_DX_MAX_SRVIEWS 128
|
#define SVGA3D_DX_MAX_SRVIEWS 128
|
||||||
#define SVGA3D_DX_MAX_CONSTBUFFERS 16
|
#define SVGA3D_DX_MAX_CONSTBUFFERS 16
|
||||||
#define SVGA3D_DX_MAX_SAMPLERS 16
|
#define SVGA3D_DX_MAX_SAMPLERS 16
|
||||||
|
|
||||||
/* Id limits */
|
#define SVGA3D_DX_MAX_CONSTBUF_BINDING_SIZE (4096 * 4 * (uint32)sizeof(uint32))
|
||||||
static const uint32 SVGA3dBlendObjectCountPerContext = 4096;
|
|
||||||
static const uint32 SVGA3dDepthStencilObjectCountPerContext = 4096;
|
|
||||||
|
|
||||||
typedef uint32 SVGA3dSurfaceId;
|
|
||||||
typedef uint32 SVGA3dShaderResourceViewId;
|
typedef uint32 SVGA3dShaderResourceViewId;
|
||||||
typedef uint32 SVGA3dRenderTargetViewId;
|
typedef uint32 SVGA3dRenderTargetViewId;
|
||||||
typedef uint32 SVGA3dDepthStencilViewId;
|
typedef uint32 SVGA3dDepthStencilViewId;
|
||||||
|
@ -193,20 +214,6 @@ struct SVGA3dCmdDXInvalidateContext {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
|
SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
|
||||||
|
|
||||||
typedef
|
|
||||||
#include "vmware_pack_begin.h"
|
|
||||||
struct SVGA3dReplyFormatData {
|
|
||||||
uint32 formatSupport;
|
|
||||||
uint32 msaa2xQualityLevels:5;
|
|
||||||
uint32 msaa4xQualityLevels:5;
|
|
||||||
uint32 msaa8xQualityLevels:5;
|
|
||||||
uint32 msaa16xQualityLevels:5;
|
|
||||||
uint32 msaa32xQualityLevels:5;
|
|
||||||
uint32 pad:7;
|
|
||||||
}
|
|
||||||
#include "vmware_pack_end.h"
|
|
||||||
SVGA3dReplyFormatData;
|
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDXSetSingleConstantBuffer {
|
struct SVGA3dCmdDXSetSingleConstantBuffer {
|
||||||
|
@ -623,6 +630,28 @@ struct SVGA3dCmdDXPredCopy {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
|
SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXPredConvertRegion {
|
||||||
|
SVGA3dSurfaceId dstSid;
|
||||||
|
uint32 dstSubResource;
|
||||||
|
SVGA3dBox destBox;
|
||||||
|
SVGA3dSurfaceId srcSid;
|
||||||
|
uint32 srcSubResource;
|
||||||
|
SVGA3dBox srcBox;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXPredConvertRegion; /* SVGA_3D_CMD_DX_PRED_CONVERT_REGION */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXPredConvert {
|
||||||
|
SVGA3dSurfaceId dstSid;
|
||||||
|
SVGA3dSurfaceId srcSid;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXPredConvert; /* SVGA_3D_CMD_DX_PRED_CONVERT */
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDXBufferCopy {
|
struct SVGA3dCmdDXBufferCopy {
|
||||||
|
@ -636,23 +665,57 @@ struct SVGA3dCmdDXBufferCopy {
|
||||||
SVGA3dCmdDXBufferCopy;
|
SVGA3dCmdDXBufferCopy;
|
||||||
/* SVGA_3D_CMD_DX_BUFFER_COPY */
|
/* SVGA_3D_CMD_DX_BUFFER_COPY */
|
||||||
|
|
||||||
typedef uint32 SVGA3dDXStretchBltMode;
|
/*
|
||||||
#define SVGADX_STRETCHBLT_LINEAR (1 << 0)
|
* Perform a surface copy between a multisample, and a non-multisampled
|
||||||
#define SVGADX_STRETCHBLT_FORCE_SRC_SRGB (1 << 1)
|
* surface.
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
SVGA3dSurfaceId dstSid;
|
||||||
|
uint32 dstSubResource;
|
||||||
|
SVGA3dSurfaceId srcSid;
|
||||||
|
uint32 srcSubResource;
|
||||||
|
SVGA3dSurfaceFormat copyFormat;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXResolveCopy; /* SVGA_3D_CMD_DX_RESOLVE_COPY */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Perform a predicated surface copy between a multisample, and a
|
||||||
|
* non-multisampled surface.
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
SVGA3dSurfaceId dstSid;
|
||||||
|
uint32 dstSubResource;
|
||||||
|
SVGA3dSurfaceId srcSid;
|
||||||
|
uint32 srcSubResource;
|
||||||
|
SVGA3dSurfaceFormat copyFormat;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXPredResolveCopy; /* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY */
|
||||||
|
|
||||||
|
typedef uint32 SVGA3dDXPresentBltMode;
|
||||||
|
#define SVGADX_PRESENTBLT_LINEAR (1 << 0)
|
||||||
|
#define SVGADX_PRESENTBLT_FORCE_SRC_SRGB (1 << 1)
|
||||||
|
#define SVGADX_PRESENTBLT_FORCE_SRC_XRBIAS (1 << 2)
|
||||||
|
#define SVGADX_PRESENTBLT_MODE_MAX (1 << 3)
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDXStretchBlt {
|
struct SVGA3dCmdDXPresentBlt {
|
||||||
SVGA3dSurfaceId srcSid;
|
SVGA3dSurfaceId srcSid;
|
||||||
uint32 srcSubResource;
|
uint32 srcSubResource;
|
||||||
SVGA3dSurfaceId dstSid;
|
SVGA3dSurfaceId dstSid;
|
||||||
uint32 destSubResource;
|
uint32 destSubResource;
|
||||||
SVGA3dBox boxSrc;
|
SVGA3dBox boxSrc;
|
||||||
SVGA3dBox boxDest;
|
SVGA3dBox boxDest;
|
||||||
SVGA3dDXStretchBltMode mode;
|
SVGA3dDXPresentBltMode mode;
|
||||||
}
|
}
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXStretchBlt; /* SVGA_3D_CMD_DX_STRETCHBLT */
|
SVGA3dCmdDXPresentBlt; /* SVGA_3D_CMD_DX_PRESENTBLT*/
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
|
@ -662,26 +725,6 @@ struct SVGA3dCmdDXGenMips {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
|
SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
|
||||||
|
|
||||||
/*
|
|
||||||
* Defines a resource/DX surface. Resources share the surfaceId namespace.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
typedef
|
|
||||||
#include "vmware_pack_begin.h"
|
|
||||||
struct SVGA3dCmdDefineGBSurface_v2 {
|
|
||||||
uint32 sid;
|
|
||||||
SVGA3dSurfaceFlags surfaceFlags;
|
|
||||||
SVGA3dSurfaceFormat format;
|
|
||||||
uint32 numMipLevels;
|
|
||||||
uint32 multisampleCount;
|
|
||||||
SVGA3dTextureFilter autogenFilter;
|
|
||||||
SVGA3dSize size;
|
|
||||||
uint32 arraySize;
|
|
||||||
uint32 pad;
|
|
||||||
}
|
|
||||||
#include "vmware_pack_end.h"
|
|
||||||
SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Update a sub-resource in a guest-backed resource.
|
* Update a sub-resource in a guest-backed resource.
|
||||||
* (Inform the device that the guest-contents have been updated.)
|
* (Inform the device that the guest-contents have been updated.)
|
||||||
|
@ -725,7 +768,8 @@ SVGA3dCmdDXInvalidateSubResource; /* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Raw byte wise transfer from a buffer surface into another surface
|
* Raw byte wise transfer from a buffer surface into another surface
|
||||||
* of the requested box.
|
* of the requested box. Supported if 3d is enabled and SVGA_CAP_DX
|
||||||
|
* is set. This command does not take a context.
|
||||||
*/
|
*/
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
|
@ -774,6 +818,93 @@ struct SVGA3dCmdDXSurfaceCopyAndReadback {
|
||||||
SVGA3dCmdDXSurfaceCopyAndReadback;
|
SVGA3dCmdDXSurfaceCopyAndReadback;
|
||||||
/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
|
/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SVGA_DX_HINT_NONE: Does nothing.
|
||||||
|
*
|
||||||
|
* SVGA_DX_HINT_PREFETCH_OBJECT:
|
||||||
|
* SVGA_DX_HINT_PREEVICT_OBJECT:
|
||||||
|
* Consumes a SVGAObjectRef, and hints that the host should consider
|
||||||
|
* fetching/evicting the specified object.
|
||||||
|
*
|
||||||
|
* An id of SVGA3D_INVALID_ID can be used if the guest isn't sure
|
||||||
|
* what object was affected. (For instance, if the guest knows that
|
||||||
|
* it is about to evict a DXShader, but doesn't know precisely which one,
|
||||||
|
* the device can still use this to help limit it's search, or track
|
||||||
|
* how many page-outs have happened.)
|
||||||
|
*
|
||||||
|
* SVGA_DX_HINT_PREFETCH_COBJECT:
|
||||||
|
* SVGA_DX_HINT_PREEVICT_COBJECT:
|
||||||
|
* Same as the above, except they consume an SVGACObjectRef.
|
||||||
|
*/
|
||||||
|
typedef uint32 SVGADXHintId;
|
||||||
|
#define SVGA_DX_HINT_NONE 0
|
||||||
|
#define SVGA_DX_HINT_PREFETCH_OBJECT 1
|
||||||
|
#define SVGA_DX_HINT_PREEVICT_OBJECT 2
|
||||||
|
#define SVGA_DX_HINT_PREFETCH_COBJECT 3
|
||||||
|
#define SVGA_DX_HINT_PREEVICT_COBJECT 4
|
||||||
|
#define SVGA_DX_HINT_MAX 5
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGAObjectRef {
|
||||||
|
SVGAOTableType type;
|
||||||
|
uint32 id;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGAObjectRef;
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGACObjectRef {
|
||||||
|
SVGACOTableType type;
|
||||||
|
uint32 cid;
|
||||||
|
uint32 id;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGACObjectRef;
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXHint {
|
||||||
|
SVGADXHintId hintId;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Followed by variable sized data depending on the hintId.
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXHint;
|
||||||
|
/* SVGA_3D_CMD_DX_HINT */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXBufferUpdate {
|
||||||
|
SVGA3dSurfaceId sid;
|
||||||
|
uint32 x;
|
||||||
|
uint32 width;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXBufferUpdate;
|
||||||
|
/* SVGA_3D_CMD_DX_BUFFER_UPDATE */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXSetConstantBufferOffset {
|
||||||
|
uint32 slot;
|
||||||
|
uint32 offsetInBytes;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXSetConstantBufferOffset;
|
||||||
|
|
||||||
|
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetVSConstantBufferOffset;
|
||||||
|
/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET */
|
||||||
|
|
||||||
|
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetPSConstantBufferOffset;
|
||||||
|
/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET */
|
||||||
|
|
||||||
|
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetGSConstantBufferOffset;
|
||||||
|
/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET */
|
||||||
|
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
|
@ -790,7 +921,7 @@ struct {
|
||||||
uint32 firstArraySlice;
|
uint32 firstArraySlice;
|
||||||
uint32 mipLevels;
|
uint32 mipLevels;
|
||||||
uint32 arraySize;
|
uint32 arraySize;
|
||||||
} tex;
|
} tex; /* 1d, 2d, 3d, cube */
|
||||||
struct {
|
struct {
|
||||||
uint32 firstElement;
|
uint32 firstElement;
|
||||||
uint32 numElements;
|
uint32 numElements;
|
||||||
|
@ -845,6 +976,7 @@ struct SVGA3dRenderTargetViewDesc {
|
||||||
struct {
|
struct {
|
||||||
uint32 firstElement;
|
uint32 firstElement;
|
||||||
uint32 numElements;
|
uint32 numElements;
|
||||||
|
uint32 padding0;
|
||||||
} buffer;
|
} buffer;
|
||||||
struct {
|
struct {
|
||||||
uint32 mipSlice;
|
uint32 mipSlice;
|
||||||
|
@ -965,9 +1097,6 @@ SVGA3dInputElementDesc;
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
/*
|
|
||||||
* XXX: How many of these can there be?
|
|
||||||
*/
|
|
||||||
uint32 elid;
|
uint32 elid;
|
||||||
uint32 numDescs;
|
uint32 numDescs;
|
||||||
SVGA3dInputElementDesc desc[32];
|
SVGA3dInputElementDesc desc[32];
|
||||||
|
@ -1008,7 +1137,7 @@ struct SVGA3dDXBlendStatePerRT {
|
||||||
uint8 srcBlendAlpha;
|
uint8 srcBlendAlpha;
|
||||||
uint8 destBlendAlpha;
|
uint8 destBlendAlpha;
|
||||||
uint8 blendOpAlpha;
|
uint8 blendOpAlpha;
|
||||||
uint8 renderTargetWriteMask;
|
SVGA3dColorWriteEnable renderTargetWriteMask;
|
||||||
uint8 logicOpEnable;
|
uint8 logicOpEnable;
|
||||||
uint8 logicOp;
|
uint8 logicOp;
|
||||||
uint16 pad0;
|
uint16 pad0;
|
||||||
|
@ -1126,7 +1255,7 @@ struct {
|
||||||
float slopeScaledDepthBias;
|
float slopeScaledDepthBias;
|
||||||
uint8 depthClipEnable;
|
uint8 depthClipEnable;
|
||||||
uint8 scissorEnable;
|
uint8 scissorEnable;
|
||||||
uint8 multisampleEnable;
|
SVGA3dMultisampleRastEnable multisampleEnable;
|
||||||
uint8 antialiasedLineEnable;
|
uint8 antialiasedLineEnable;
|
||||||
float lineWidth;
|
float lineWidth;
|
||||||
uint8 lineStippleEnable;
|
uint8 lineStippleEnable;
|
||||||
|
@ -1153,7 +1282,7 @@ struct SVGA3dCmdDXDefineRasterizerState {
|
||||||
float slopeScaledDepthBias;
|
float slopeScaledDepthBias;
|
||||||
uint8 depthClipEnable;
|
uint8 depthClipEnable;
|
||||||
uint8 scissorEnable;
|
uint8 scissorEnable;
|
||||||
uint8 multisampleEnable;
|
SVGA3dMultisampleRastEnable multisampleEnable;
|
||||||
uint8 antialiasedLineEnable;
|
uint8 antialiasedLineEnable;
|
||||||
float lineWidth;
|
float lineWidth;
|
||||||
uint8 lineStippleEnable;
|
uint8 lineStippleEnable;
|
||||||
|
@ -1223,21 +1352,6 @@ struct SVGA3dCmdDXDestroySamplerState {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
|
SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
|
||||||
|
|
||||||
/*
|
|
||||||
*/
|
|
||||||
typedef
|
|
||||||
#include "vmware_pack_begin.h"
|
|
||||||
struct SVGA3dSignatureEntry {
|
|
||||||
uint8 systemValue;
|
|
||||||
uint8 reg; /* register is a reserved word */
|
|
||||||
uint16 mask;
|
|
||||||
uint8 registerComponentType;
|
|
||||||
uint8 minPrecision;
|
|
||||||
uint16 pad0;
|
|
||||||
}
|
|
||||||
#include "vmware_pack_end.h"
|
|
||||||
SVGA3dSignatureEntry;
|
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDXDefineShader {
|
struct SVGA3dCmdDXDefineShader {
|
||||||
|
@ -1255,12 +1369,7 @@ struct SVGACOTableDXShaderEntry {
|
||||||
uint32 sizeInBytes;
|
uint32 sizeInBytes;
|
||||||
uint32 offsetInBytes;
|
uint32 offsetInBytes;
|
||||||
SVGAMobId mobid;
|
SVGAMobId mobid;
|
||||||
uint32 numInputSignatureEntries;
|
uint32 pad[4];
|
||||||
uint32 numOutputSignatureEntries;
|
|
||||||
|
|
||||||
uint32 numPatchConstantSignatureEntries;
|
|
||||||
|
|
||||||
uint32 pad;
|
|
||||||
}
|
}
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGACOTableDXShaderEntry;
|
SVGACOTableDXShaderEntry;
|
||||||
|
@ -1284,6 +1393,25 @@ struct SVGA3dCmdDXBindShader {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
|
SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXBindAllShader {
|
||||||
|
uint32 cid;
|
||||||
|
SVGAMobId mobid;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXBindAllShader; /* SVGA_3D_CMD_DX_BIND_ALL_SHADER */
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXCondBindAllShader {
|
||||||
|
uint32 cid;
|
||||||
|
SVGAMobId testMobid;
|
||||||
|
SVGAMobId mobid;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXCondBindAllShader; /* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The maximum number of streamout decl's in each streamout entry.
|
* The maximum number of streamout decl's in each streamout entry.
|
||||||
*/
|
*/
|
||||||
|
@ -1357,7 +1485,6 @@ SVGA3dCmdDXMobFence64; /* SVGA_3D_CMD_DX_MOB_FENCE_64 */
|
||||||
*
|
*
|
||||||
* This command allows the guest to bind a mob to a context-object table.
|
* This command allows the guest to bind a mob to a context-object table.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDXSetCOTable {
|
struct SVGA3dCmdDXSetCOTable {
|
||||||
|
@ -1369,6 +1496,26 @@ struct SVGA3dCmdDXSetCOTable {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
|
SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Guests using SVGA_3D_CMD_DX_GROW_COTABLE are promising that
|
||||||
|
* the new COTable contains the same contents as the old one, except possibly
|
||||||
|
* for some new invalid entries at the end.
|
||||||
|
*
|
||||||
|
* If there is an old cotable mob bound, it also has to still be valid.
|
||||||
|
*
|
||||||
|
* (Otherwise, guests should use the DXSetCOTableBase command.)
|
||||||
|
*/
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dCmdDXGrowCOTable {
|
||||||
|
uint32 cid;
|
||||||
|
uint32 mobid;
|
||||||
|
SVGACOTableType type;
|
||||||
|
uint32 validSizeInBytes;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dCmdDXGrowCOTable; /* SVGA_3D_CMD_DX_GROW_COTABLE */
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCmdDXReadbackCOTable {
|
struct SVGA3dCmdDXReadbackCOTable {
|
||||||
|
@ -1472,7 +1619,7 @@ struct SVGADXContextMobFormat {
|
||||||
SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
|
SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
|
||||||
|
|
||||||
SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
|
SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
|
||||||
uint32 pad7[381];
|
uint32 pad7[380];
|
||||||
}
|
}
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGADXContextMobFormat;
|
SVGADXContextMobFormat;
|
||||||
|
|
|
@ -63,7 +63,9 @@
|
||||||
* Maximum size in dwords of shader text the SVGA device will allow.
|
* Maximum size in dwords of shader text the SVGA device will allow.
|
||||||
* Currently 8 MB.
|
* Currently 8 MB.
|
||||||
*/
|
*/
|
||||||
#define SVGA3D_MAX_SHADER_MEMORY (8 * 1024 * 1024 / sizeof(uint32))
|
#define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024)
|
||||||
|
#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
|
||||||
|
sizeof(uint32))
|
||||||
|
|
||||||
#define SVGA3D_MAX_CLIP_PLANES 6
|
#define SVGA3D_MAX_CLIP_PLANES 6
|
||||||
|
|
||||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -45,9 +45,21 @@
|
||||||
|
|
||||||
#define SVGA3D_INVALID_ID ((uint32)-1)
|
#define SVGA3D_INVALID_ID ((uint32)-1)
|
||||||
|
|
||||||
|
typedef uint8 SVGABool8; /* 8-bit Bool definition */
|
||||||
typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
|
typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
|
||||||
typedef uint32 SVGA3dColor; /* a, r, g, b */
|
typedef uint32 SVGA3dColor; /* a, r, g, b */
|
||||||
|
|
||||||
|
typedef uint32 SVGA3dSurfaceId;
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct {
|
||||||
|
uint32 numerator;
|
||||||
|
uint32 denominator;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dFraction64;
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dCopyRect {
|
struct SVGA3dCopyRect {
|
||||||
|
@ -146,7 +158,7 @@ typedef enum SVGA3dSurfaceFormat {
|
||||||
SVGA3D_BUMPU8V8 = 20,
|
SVGA3D_BUMPU8V8 = 20,
|
||||||
SVGA3D_BUMPL6V5U5 = 21,
|
SVGA3D_BUMPL6V5U5 = 21,
|
||||||
SVGA3D_BUMPX8L8V8U8 = 22,
|
SVGA3D_BUMPX8L8V8U8 = 22,
|
||||||
SVGA3D_BUMPL8V8U8 = 23,
|
SVGA3D_FORMAT_DEAD1 = 23,
|
||||||
|
|
||||||
SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
|
SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
|
||||||
SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
|
SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
|
||||||
|
@ -205,8 +217,8 @@ typedef enum SVGA3dSurfaceFormat {
|
||||||
SVGA3D_R32G32_SINT = 59,
|
SVGA3D_R32G32_SINT = 59,
|
||||||
SVGA3D_R32G8X24_TYPELESS = 60,
|
SVGA3D_R32G8X24_TYPELESS = 60,
|
||||||
SVGA3D_D32_FLOAT_S8X24_UINT = 61,
|
SVGA3D_D32_FLOAT_S8X24_UINT = 61,
|
||||||
SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
|
SVGA3D_R32_FLOAT_X8X24 = 62,
|
||||||
SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
|
SVGA3D_X32_G8X24_UINT = 63,
|
||||||
SVGA3D_R10G10B10A2_TYPELESS = 64,
|
SVGA3D_R10G10B10A2_TYPELESS = 64,
|
||||||
SVGA3D_R10G10B10A2_UINT = 65,
|
SVGA3D_R10G10B10A2_UINT = 65,
|
||||||
SVGA3D_R11G11B10_FLOAT = 66,
|
SVGA3D_R11G11B10_FLOAT = 66,
|
||||||
|
@ -224,8 +236,8 @@ typedef enum SVGA3dSurfaceFormat {
|
||||||
SVGA3D_R32_SINT = 78,
|
SVGA3D_R32_SINT = 78,
|
||||||
SVGA3D_R24G8_TYPELESS = 79,
|
SVGA3D_R24G8_TYPELESS = 79,
|
||||||
SVGA3D_D24_UNORM_S8_UINT = 80,
|
SVGA3D_D24_UNORM_S8_UINT = 80,
|
||||||
SVGA3D_R24_UNORM_X8_TYPELESS = 81,
|
SVGA3D_R24_UNORM_X8 = 81,
|
||||||
SVGA3D_X24_TYPELESS_G8_UINT = 82,
|
SVGA3D_X24_G8_UINT = 82,
|
||||||
SVGA3D_R8G8_TYPELESS = 83,
|
SVGA3D_R8G8_TYPELESS = 83,
|
||||||
SVGA3D_R8G8_UNORM = 84,
|
SVGA3D_R8G8_UNORM = 84,
|
||||||
SVGA3D_R8G8_UINT = 85,
|
SVGA3D_R8G8_UINT = 85,
|
||||||
|
@ -297,92 +309,114 @@ typedef enum SVGA3dSurfaceFormat {
|
||||||
SVGA3D_FORMAT_MAX
|
SVGA3D_FORMAT_MAX
|
||||||
} SVGA3dSurfaceFormat;
|
} SVGA3dSurfaceFormat;
|
||||||
|
|
||||||
typedef enum SVGA3dSurfaceFlags {
|
/*
|
||||||
SVGA3D_SURFACE_CUBEMAP = (1 << 0),
|
* SVGA3d Surface Flags --
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_CUBEMAP (1 << 0)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* HINT flags are not enforced by the device but are useful for
|
* HINT flags are not enforced by the device but are useful for
|
||||||
* performance.
|
* performance.
|
||||||
*/
|
*/
|
||||||
SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
|
#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1)
|
||||||
SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
|
#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2)
|
||||||
SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
|
#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3)
|
||||||
SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
|
#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4)
|
||||||
SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
|
#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5)
|
||||||
SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
|
#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6)
|
||||||
SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
|
#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7)
|
||||||
SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
|
#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8)
|
||||||
SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
|
#define SVGA3D_SURFACE_MASKABLE_ANTIALIAS (CONST64U(1) << 9)
|
||||||
SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
|
#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10)
|
||||||
SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11),
|
|
||||||
|
|
||||||
/*
|
#define SVGA3D_SURFACE_DECODE_RENDERTARGET (CONST64U(1) << 11)
|
||||||
* Is this surface using a base-level pitch for it's mob backing?
|
|
||||||
*
|
|
||||||
* This flag is not intended to be set by guest-drivers, but is instead
|
|
||||||
* set by the device when the surface is bound to a mob with a specified
|
|
||||||
* pitch.
|
|
||||||
*/
|
|
||||||
SVGA3D_SURFACE_MOB_PITCH = (1 << 12),
|
|
||||||
|
|
||||||
SVGA3D_SURFACE_INACTIVE = (1 << 13),
|
/*
|
||||||
SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14),
|
* Is this surface using a base-level pitch for it's mob backing?
|
||||||
SVGA3D_SURFACE_VOLUME = (1 << 15),
|
*
|
||||||
|
* This flag is not intended to be set by guest-drivers, but is instead
|
||||||
|
* set by the device when the surface is bound to a mob with a specified
|
||||||
|
* pitch.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12)
|
||||||
|
|
||||||
/*
|
#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13)
|
||||||
* Required to be set on a surface to bind it to a screen target.
|
#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14)
|
||||||
*/
|
#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15)
|
||||||
SVGA3D_SURFACE_SCREENTARGET = (1 << 16),
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Align images in the guest-backing mob to 16-bytes.
|
* Required to be set on a surface to bind it to a screen target.
|
||||||
*/
|
*/
|
||||||
SVGA3D_SURFACE_ALIGN16 = (1 << 17),
|
#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16)
|
||||||
|
|
||||||
SVGA3D_SURFACE_1D = (1 << 18),
|
/*
|
||||||
SVGA3D_SURFACE_ARRAY = (1 << 19),
|
* Align images in the guest-backing mob to 16-bytes.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17)
|
||||||
|
|
||||||
/*
|
#define SVGA3D_SURFACE_1D (CONST64U(1) << 18)
|
||||||
* Bind flags.
|
#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19)
|
||||||
* These are enforced for any surface defined with DefineGBSurface_v2.
|
|
||||||
*/
|
|
||||||
SVGA3D_SURFACE_BIND_VERTEX_BUFFER = (1 << 20),
|
|
||||||
SVGA3D_SURFACE_BIND_INDEX_BUFFER = (1 << 21),
|
|
||||||
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER = (1 << 22),
|
|
||||||
SVGA3D_SURFACE_BIND_SHADER_RESOURCE = (1 << 23),
|
|
||||||
SVGA3D_SURFACE_BIND_RENDER_TARGET = (1 << 24),
|
|
||||||
SVGA3D_SURFACE_BIND_DEPTH_STENCIL = (1 << 25),
|
|
||||||
SVGA3D_SURFACE_BIND_STREAM_OUTPUT = (1 << 26),
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* A note on staging flags:
|
* Bind flags.
|
||||||
*
|
* These are enforced for any surface defined with DefineGBSurface_v2.
|
||||||
* The STAGING flags notes that the surface will not be used directly by the
|
*/
|
||||||
* drawing pipeline, i.e. that it will not be bound to any bind point.
|
#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20)
|
||||||
* Staging surfaces may be used by copy operations to move data in and out
|
#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21)
|
||||||
* of other surfaces.
|
#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22)
|
||||||
*
|
#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23)
|
||||||
* The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
|
#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24)
|
||||||
* updates indirectly, i.e. the surface will not be updated directly, but
|
#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25)
|
||||||
* will receive copies from staging surfaces.
|
#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26)
|
||||||
*/
|
|
||||||
SVGA3D_SURFACE_STAGING_UPLOAD = (1 << 27),
|
|
||||||
SVGA3D_SURFACE_STAGING_DOWNLOAD = (1 << 28),
|
|
||||||
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE = (1 << 29),
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Setting this flag allow this surface to be used with the
|
* The STAGING flags notes that the surface will not be used directly by the
|
||||||
* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
|
* drawing pipeline, i.e. that it will not be bound to any bind point.
|
||||||
* buffer surfaces, an no bind flags are allowed to be set on surfaces
|
* Staging surfaces may be used by copy operations to move data in and out
|
||||||
* with this flag.
|
* of other surfaces. No bind flags may be set on surfaces with this flag.
|
||||||
*/
|
*
|
||||||
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER = (1 << 30),
|
* The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
|
||||||
|
* updates indirectly, i.e. the surface will not be updated directly, but
|
||||||
|
* will receive copies from staging surfaces.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27)
|
||||||
|
#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28)
|
||||||
|
#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Marker for the last defined bit.
|
* Setting this flag allow this surface to be used with the
|
||||||
*/
|
* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
|
||||||
SVGA3D_SURFACE_FLAG_MAX = (1 << 31),
|
* buffer surfaces, and no bind flags are allowed to be set on surfaces
|
||||||
} SVGA3dSurfaceFlags;
|
* with this flag.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reserved for video operations.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Specifies that a surface is multisample, and therefore requires the full
|
||||||
|
* mob-backing to store all the samples.
|
||||||
|
*/
|
||||||
|
#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
|
||||||
|
|
||||||
|
#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 33)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Surface flags types:
|
||||||
|
*
|
||||||
|
* SVGA3dSurface1Flags: Lower 32-bits of flags.
|
||||||
|
* SVGA3dSurface2Flags: Upper 32-bits of flags.
|
||||||
|
* SVGA3dSurfaceAllFlags: Full 64-bits of flags.
|
||||||
|
*/
|
||||||
|
typedef uint32 SVGA3dSurface1Flags;
|
||||||
|
typedef uint32 SVGA3dSurface2Flags;
|
||||||
|
typedef uint64 SVGA3dSurfaceAllFlags;
|
||||||
|
|
||||||
|
#define SVGA3D_SURFACE_FLAGS1_MASK ((uint64_t)MAX_UINT32)
|
||||||
|
#define SVGA3D_SURFACE_FLAGS2_MASK (MAX_UINT64 & ~SVGA3D_SURFACE_FLAGS1_MASK)
|
||||||
|
|
||||||
#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
|
#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
|
||||||
( SVGA3D_SURFACE_MOB_PITCH | \
|
( SVGA3D_SURFACE_MOB_PITCH | \
|
||||||
|
@ -393,29 +427,41 @@ typedef enum SVGA3dSurfaceFlags {
|
||||||
SVGA3D_SURFACE_STAGING_UPLOAD | \
|
SVGA3D_SURFACE_STAGING_UPLOAD | \
|
||||||
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
|
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
|
||||||
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
|
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
|
||||||
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
|
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
|
||||||
|
SVGA3D_SURFACE_MULTISAMPLE \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \
|
||||||
|
( SVGA3D_SURFACE_1D | \
|
||||||
|
SVGA3D_SURFACE_MULTISAMPLE \
|
||||||
)
|
)
|
||||||
|
|
||||||
#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
|
#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
|
||||||
( SVGA3D_SURFACE_CUBEMAP | \
|
( SVGA3D_SURFACE_CUBEMAP | \
|
||||||
SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
|
SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
|
||||||
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
||||||
SVGA3D_SURFACE_DECODE_RENDERTARGET | \
|
|
||||||
SVGA3D_SURFACE_VOLUME | \
|
SVGA3D_SURFACE_VOLUME | \
|
||||||
SVGA3D_SURFACE_1D | \
|
SVGA3D_SURFACE_1D | \
|
||||||
SVGA3D_SURFACE_ARRAY | \
|
|
||||||
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
|
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
|
||||||
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
|
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
|
||||||
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
|
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
|
||||||
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
|
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
|
||||||
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
|
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
|
||||||
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
|
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
|
||||||
|
SVGA3D_SURFACE_MULTISAMPLE \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
|
||||||
|
( SVGA3D_SURFACE_CUBEMAP | \
|
||||||
|
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
||||||
|
SVGA3D_SURFACE_VOLUME | \
|
||||||
|
SVGA3D_SURFACE_1D | \
|
||||||
|
SVGA3D_SURFACE_MULTISAMPLE \
|
||||||
)
|
)
|
||||||
|
|
||||||
#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
|
#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
|
||||||
( SVGA3D_SURFACE_CUBEMAP | \
|
( SVGA3D_SURFACE_CUBEMAP | \
|
||||||
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
||||||
SVGA3D_SURFACE_DECODE_RENDERTARGET | \
|
|
||||||
SVGA3D_SURFACE_VOLUME | \
|
SVGA3D_SURFACE_VOLUME | \
|
||||||
SVGA3D_SURFACE_1D | \
|
SVGA3D_SURFACE_1D | \
|
||||||
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
|
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
|
||||||
|
@ -427,12 +473,36 @@ typedef enum SVGA3dSurfaceFlags {
|
||||||
SVGA3D_SURFACE_STAGING_UPLOAD | \
|
SVGA3D_SURFACE_STAGING_UPLOAD | \
|
||||||
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
|
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
|
||||||
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
|
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
|
||||||
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
|
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
|
||||||
|
SVGA3D_SURFACE_MULTISAMPLE \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
|
||||||
|
( SVGA3D_SURFACE_CUBEMAP | \
|
||||||
|
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
||||||
|
SVGA3D_SURFACE_VOLUME | \
|
||||||
|
SVGA3D_SURFACE_1D | \
|
||||||
|
SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
|
||||||
|
SVGA3D_SURFACE_ARRAY | \
|
||||||
|
SVGA3D_SURFACE_MULTISAMPLE | \
|
||||||
|
SVGA3D_SURFACE_MOB_PITCH \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \
|
||||||
|
( SVGA3D_SURFACE_CUBEMAP | \
|
||||||
|
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
|
||||||
|
SVGA3D_SURFACE_VOLUME | \
|
||||||
|
SVGA3D_SURFACE_1D | \
|
||||||
|
SVGA3D_SURFACE_SCREENTARGET | \
|
||||||
|
SVGA3D_SURFACE_MOB_PITCH \
|
||||||
)
|
)
|
||||||
|
|
||||||
#define SVGA3D_SURFACE_DX_ONLY_MASK \
|
#define SVGA3D_SURFACE_DX_ONLY_MASK \
|
||||||
( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
|
( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
|
||||||
|
SVGA3D_SURFACE_STAGING_UPLOAD | \
|
||||||
|
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
|
||||||
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
|
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
|
||||||
|
)
|
||||||
|
|
||||||
#define SVGA3D_SURFACE_STAGING_MASK \
|
#define SVGA3D_SURFACE_STAGING_MASK \
|
||||||
( SVGA3D_SURFACE_STAGING_UPLOAD | \
|
( SVGA3D_SURFACE_STAGING_UPLOAD | \
|
||||||
|
@ -488,7 +558,7 @@ typedef enum {
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that this format can be converted to any RGB format for which
|
* Indicates that this format can be converted to any RGB format for which
|
||||||
* SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
|
* SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
|
SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
|
||||||
|
|
||||||
|
@ -499,22 +569,22 @@ typedef enum {
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicated that this format can be read as an SRGB texture (meaning that the
|
* Indicated that this format can be read as an SRGB texture (meaning that the
|
||||||
* sampler will linearize the looked up data)
|
* sampler will linearize the looked up data).
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
|
SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that this format can be used in the bumpmap instructions
|
* Indicates that this format can be used in the bumpmap instructions.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
|
SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that this format can be sampled by the displacement map sampler
|
* Indicates that this format can be sampled by the displacement map sampler.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_DMAP = 0x00020000,
|
SVGA3DFORMAT_OP_DMAP = 0x00020000,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that this format cannot be used with texture filtering
|
* Indicates that this format cannot be used with texture filtering.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
|
SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
|
||||||
|
|
||||||
|
@ -531,18 +601,18 @@ typedef enum {
|
||||||
SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
|
SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that this format cannot be used with alpha blending
|
* Indicates that this format cannot be used with alpha blending.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
|
SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that the device can auto-generated sublevels for resources
|
* Indicates that the device can auto-generated sublevels for resources
|
||||||
* of this format
|
* of this format.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
|
SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Indicates that this format can be used by vertex texture sampler
|
* Indicates that this format can be used by vertex texture sampler.
|
||||||
*/
|
*/
|
||||||
SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
|
SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
|
||||||
|
|
||||||
|
@ -1502,7 +1572,6 @@ union SVGADXQueryResultUnion {
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGADXQueryResultUnion;
|
SVGADXQueryResultUnion;
|
||||||
|
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
|
SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
|
||||||
SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
|
SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
|
||||||
|
@ -1534,9 +1603,9 @@ typedef
|
||||||
struct {
|
struct {
|
||||||
union {
|
union {
|
||||||
struct {
|
struct {
|
||||||
uint16 function; /* SVGA3dFogFunction */
|
uint16 function; /* SVGA3dFogFunction */
|
||||||
uint8 type; /* SVGA3dFogType */
|
uint8 type; /* SVGA3dFogType */
|
||||||
uint8 base; /* SVGA3dFogBase */
|
uint8 base; /* SVGA3dFogBase */
|
||||||
};
|
};
|
||||||
uint32 uintValue;
|
uint32 uintValue;
|
||||||
};
|
};
|
||||||
|
@ -1548,17 +1617,25 @@ SVGA3dFogMode;
|
||||||
* Uniquely identify one image (a 1D/2D/3D array) from a surface. This
|
* Uniquely identify one image (a 1D/2D/3D array) from a surface. This
|
||||||
* is a surface ID as well as face/mipmap indices.
|
* is a surface ID as well as face/mipmap indices.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct SVGA3dSurfaceImageId {
|
struct SVGA3dSurfaceImageId {
|
||||||
uint32 sid;
|
uint32 sid;
|
||||||
uint32 face;
|
uint32 face;
|
||||||
uint32 mipmap;
|
uint32 mipmap;
|
||||||
}
|
}
|
||||||
#include "vmware_pack_end.h"
|
#include "vmware_pack_end.h"
|
||||||
SVGA3dSurfaceImageId;
|
SVGA3dSurfaceImageId;
|
||||||
|
|
||||||
|
typedef
|
||||||
|
#include "vmware_pack_begin.h"
|
||||||
|
struct SVGA3dSubSurfaceId {
|
||||||
|
uint32 sid;
|
||||||
|
uint32 subResourceId;
|
||||||
|
}
|
||||||
|
#include "vmware_pack_end.h"
|
||||||
|
SVGA3dSubSurfaceId;
|
||||||
|
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
|
@ -1583,13 +1660,18 @@ typedef enum {
|
||||||
SVGA_OTABLE_DX9_MAX = 5,
|
SVGA_OTABLE_DX9_MAX = 5,
|
||||||
|
|
||||||
SVGA_OTABLE_DXCONTEXT = 5,
|
SVGA_OTABLE_DXCONTEXT = 5,
|
||||||
SVGA_OTABLE_MAX = 6
|
SVGA_OTABLE_DX_MAX = 6,
|
||||||
} SVGAOTableType;
|
|
||||||
|
|
||||||
/*
|
SVGA_OTABLE_RESERVED1 = 6,
|
||||||
* Deprecated.
|
SVGA_OTABLE_RESERVED2 = 7,
|
||||||
*/
|
|
||||||
#define SVGA_OTABLE_COUNT 4
|
/*
|
||||||
|
* Additions to this table need to be tied to HW-version features and
|
||||||
|
* checkpointed accordingly.
|
||||||
|
*/
|
||||||
|
SVGA_OTABLE_DEVEL_MAX = 8,
|
||||||
|
SVGA_OTABLE_MAX = 8
|
||||||
|
} SVGAOTableType;
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SVGA_COTABLE_MIN = 0,
|
SVGA_COTABLE_MIN = 0,
|
||||||
|
@ -1606,7 +1688,7 @@ typedef enum {
|
||||||
SVGA_COTABLE_DXSHADER = 10,
|
SVGA_COTABLE_DXSHADER = 10,
|
||||||
SVGA_COTABLE_DX10_MAX = 11,
|
SVGA_COTABLE_DX10_MAX = 11,
|
||||||
SVGA_COTABLE_UAVIEW = 11,
|
SVGA_COTABLE_UAVIEW = 11,
|
||||||
SVGA_COTABLE_MAX
|
SVGA_COTABLE_MAX = 12,
|
||||||
} SVGACOTableType;
|
} SVGACOTableType;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1627,8 +1709,37 @@ typedef enum SVGAMobFormat {
|
||||||
SVGA3D_MOBFMT_PREDX_MAX = 7,
|
SVGA3D_MOBFMT_PREDX_MAX = 7,
|
||||||
SVGA3D_MOBFMT_EMPTY = 7,
|
SVGA3D_MOBFMT_EMPTY = 7,
|
||||||
SVGA3D_MOBFMT_MAX,
|
SVGA3D_MOBFMT_MAX,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This isn't actually used by the guest, but is a mob-format used
|
||||||
|
* internally by the SVGA device (and is therefore not binary compatible).
|
||||||
|
*/
|
||||||
|
SVGA3D_MOBFMT_HB,
|
||||||
} SVGAMobFormat;
|
} SVGAMobFormat;
|
||||||
|
|
||||||
#define SVGA3D_MOB_EMPTY_BASE 1
|
#define SVGA3D_MOB_EMPTY_BASE 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Multisample pattern types.
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum SVGA3dMSPattern {
|
||||||
|
SVGA3D_MS_PATTERN_NONE = 0,
|
||||||
|
SVGA3D_MS_PATTERN_MIN = 0,
|
||||||
|
SVGA3D_MS_PATTERN_STANDARD = 1,
|
||||||
|
SVGA3D_MS_PATTERN_CENTER = 2,
|
||||||
|
SVGA3D_MS_PATTERN_MAX = 3,
|
||||||
|
} SVGA3dMSPattern;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Precision settings for each sample.
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum SVGA3dMSQualityLevel {
|
||||||
|
SVGA3D_MS_QUALITY_NONE = 0,
|
||||||
|
SVGA3D_MS_QUALITY_MIN = 0,
|
||||||
|
SVGA3D_MS_QUALITY_FULL = 1,
|
||||||
|
SVGA3D_MS_QUALITY_MAX = 2,
|
||||||
|
} SVGA3dMSQualityLevel;
|
||||||
|
|
||||||
#endif /* _SVGA3D_TYPES_H_ */
|
#endif /* _SVGA3D_TYPES_H_ */
|
||||||
|
|
|
@ -64,16 +64,26 @@ typedef uint32 SVGAMobId;
|
||||||
#define SVGA_MAX_BITS_PER_PIXEL 32
|
#define SVGA_MAX_BITS_PER_PIXEL 32
|
||||||
#define SVGA_MAX_DEPTH 24
|
#define SVGA_MAX_DEPTH 24
|
||||||
#define SVGA_MAX_DISPLAYS 10
|
#define SVGA_MAX_DISPLAYS 10
|
||||||
|
#define SVGA_MAX_SCREEN_SIZE 8192
|
||||||
|
#define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS)
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
|
* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
|
||||||
* cursor bypass mode. This is still supported, but no new guest
|
* cursor bypass mode. This is still supported, but no new guest
|
||||||
* drivers should use it.
|
* drivers should use it.
|
||||||
*/
|
*/
|
||||||
#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
|
#define SVGA_CURSOR_ON_HIDE 0x0
|
||||||
#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
|
#define SVGA_CURSOR_ON_SHOW 0x1
|
||||||
#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
|
|
||||||
#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
|
/*
|
||||||
|
* Remove the cursor from the framebuffer
|
||||||
|
* because we need to see what's under it
|
||||||
|
*/
|
||||||
|
#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2
|
||||||
|
|
||||||
|
/* Put the cursor back in the framebuffer so the user can see it */
|
||||||
|
#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The maximum framebuffer size that can traced for guests unless the
|
* The maximum framebuffer size that can traced for guests unless the
|
||||||
|
@ -102,7 +112,10 @@ typedef uint32 SVGAMobId;
|
||||||
#define SVGA_VERSION_0 0
|
#define SVGA_VERSION_0 0
|
||||||
#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
|
#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
|
||||||
|
|
||||||
/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
|
/*
|
||||||
|
* "Invalid" value for all SVGA IDs.
|
||||||
|
* (Version ID, screen object ID, surface ID...)
|
||||||
|
*/
|
||||||
#define SVGA_ID_INVALID 0xFFFFFFFF
|
#define SVGA_ID_INVALID 0xFFFFFFFF
|
||||||
|
|
||||||
/* Port offsets, relative to BAR0 */
|
/* Port offsets, relative to BAR0 */
|
||||||
|
@ -155,7 +168,7 @@ enum {
|
||||||
SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
|
SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
|
||||||
SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
|
SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
|
||||||
SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
|
SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
|
||||||
SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
|
SVGA_REG_GUEST_ID = 23, /* (Deprecated) */
|
||||||
SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
|
SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
|
||||||
SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
|
SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
|
||||||
SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
|
SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
|
||||||
|
@ -187,7 +200,14 @@ enum {
|
||||||
SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
|
SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
|
||||||
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
|
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
|
||||||
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
|
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
|
||||||
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
|
|
||||||
|
/*
|
||||||
|
* Max primary memory.
|
||||||
|
* See SVGA_CAP_NO_BB_RESTRICTION.
|
||||||
|
*/
|
||||||
|
SVGA_REG_MAX_PRIMARY_MEM = 50,
|
||||||
|
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
|
||||||
|
|
||||||
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
|
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
|
||||||
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
|
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
|
||||||
SVGA_REG_CMD_PREPEND_LOW = 53,
|
SVGA_REG_CMD_PREPEND_LOW = 53,
|
||||||
|
@ -195,7 +215,10 @@ enum {
|
||||||
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
|
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
|
||||||
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
|
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
|
||||||
SVGA_REG_MOB_MAX_SIZE = 57,
|
SVGA_REG_MOB_MAX_SIZE = 57,
|
||||||
SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
|
SVGA_REG_BLANK_SCREEN_TARGETS = 58,
|
||||||
|
SVGA_REG_CAP2 = 59,
|
||||||
|
SVGA_REG_DEVEL_CAP = 60,
|
||||||
|
SVGA_REG_TOP = 61, /* Must be 1 more than the last register */
|
||||||
|
|
||||||
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
|
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
|
||||||
/* Next 768 (== 256*3) registers exist for colormap */
|
/* Next 768 (== 256*3) registers exist for colormap */
|
||||||
|
@ -393,6 +416,7 @@ typedef enum {
|
||||||
SVGA_CB_CONTEXT_0 = 0x0,
|
SVGA_CB_CONTEXT_0 = 0x0,
|
||||||
SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
|
SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
|
||||||
SVGA_CB_CONTEXT_MAX = 0x2,
|
SVGA_CB_CONTEXT_MAX = 0x2,
|
||||||
|
SVGA_CB_CONTEXT_HP_MAX = 0x2,
|
||||||
} SVGACBContext;
|
} SVGACBContext;
|
||||||
|
|
||||||
|
|
||||||
|
@ -449,6 +473,18 @@ typedef enum {
|
||||||
* due to an error. No IRQ is raised.
|
* due to an error. No IRQ is raised.
|
||||||
*/
|
*/
|
||||||
SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
|
SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Written by the host when the host finished a
|
||||||
|
* SVGA_DC_CMD_ASYNC_STOP_QUEUE request for this command buffer
|
||||||
|
* queue. The offset of the first byte not processed is stored in
|
||||||
|
* the errorOffset field of the command buffer header. All guest
|
||||||
|
* visible side effects of commands till that point are guaranteed
|
||||||
|
* to be finished before this is written. The
|
||||||
|
* SVGA_IRQFLAG_COMMAND_BUFFER IRQ is raised as long as the
|
||||||
|
* SVGA_CB_FLAG_NO_IRQ is not set.
|
||||||
|
*/
|
||||||
|
SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
|
||||||
} SVGACBStatus;
|
} SVGACBStatus;
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
|
@ -461,8 +497,8 @@ typedef enum {
|
||||||
typedef
|
typedef
|
||||||
#include "vmware_pack_begin.h"
|
#include "vmware_pack_begin.h"
|
||||||
struct {
|
struct {
|
||||||
volatile SVGACBStatus status;
|
volatile SVGACBStatus status; /* Modified by device. */
|
||||||
volatile uint32 errorOffset;
|
volatile uint32 errorOffset; /* Modified by device. */
|
||||||
uint64 id;
|
uint64 id;
|
||||||
SVGACBFlags flags;
|
SVGACBFlags flags;
|
||||||
uint32 length;
|
uint32 length;
|
||||||
|
@ -473,7 +509,9 @@ struct {
|
||||||
uint32 mobOffset;
|
uint32 mobOffset;
|
||||||
} mob;
|
} mob;
|
||||||
} ptr;
|
} ptr;
|
||||||
uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise */
|
uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise,
|
||||||
|
* modified by device.
|
||||||
|
*/
|
||||||
uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
|
uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
|
||||||
uint32 mustBeZero[6];
|
uint32 mustBeZero[6];
|
||||||
}
|
}
|
||||||
|
@ -484,20 +522,26 @@ typedef enum {
|
||||||
SVGA_DC_CMD_NOP = 0,
|
SVGA_DC_CMD_NOP = 0,
|
||||||
SVGA_DC_CMD_START_STOP_CONTEXT = 1,
|
SVGA_DC_CMD_START_STOP_CONTEXT = 1,
|
||||||
SVGA_DC_CMD_PREEMPT = 2,
|
SVGA_DC_CMD_PREEMPT = 2,
|
||||||
SVGA_DC_CMD_MAX = 3,
|
SVGA_DC_CMD_START_QUEUE = 3, /* Requires SVGA_CAP_HP_CMD_QUEUE */
|
||||||
SVGA_DC_CMD_FORCE_UINT = MAX_UINT32,
|
SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, /* Requires SVGA_CAP_HP_CMD_QUEUE */
|
||||||
|
SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, /* Requires SVGA_CAP_HP_CMD_QUEUE */
|
||||||
|
SVGA_DC_CMD_MAX = 6,
|
||||||
} SVGADeviceContextCmdId;
|
} SVGADeviceContextCmdId;
|
||||||
|
|
||||||
typedef struct {
|
/*
|
||||||
|
* Starts or stops both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1.
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct SVGADCCmdStartStop {
|
||||||
uint32 enable;
|
uint32 enable;
|
||||||
SVGACBContext context;
|
SVGACBContext context; /* Must be zero */
|
||||||
} SVGADCCmdStartStop;
|
} SVGADCCmdStartStop;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SVGADCCmdPreempt --
|
* SVGADCCmdPreempt --
|
||||||
*
|
*
|
||||||
* This command allows the guest to request that all command buffers
|
* This command allows the guest to request that all command buffers
|
||||||
* on the specified context be preempted that can be. After execution
|
* on SVGA_CB_CONTEXT_0 be preempted that can be. After execution
|
||||||
* of this command all command buffers that were preempted will
|
* of this command all command buffers that were preempted will
|
||||||
* already have SVGA_CB_STATUS_PREEMPTED written into the status
|
* already have SVGA_CB_STATUS_PREEMPTED written into the status
|
||||||
* field. The device might still be processing a command buffer,
|
* field. The device might still be processing a command buffer,
|
||||||
|
@ -507,11 +551,68 @@ typedef struct {
|
||||||
* command buffer header set to zero.
|
* command buffer header set to zero.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef struct {
|
typedef struct SVGADCCmdPreempt {
|
||||||
SVGACBContext context;
|
SVGACBContext context; /* Must be zero */
|
||||||
uint32 ignoreIDZero;
|
uint32 ignoreIDZero;
|
||||||
} SVGADCCmdPreempt;
|
} SVGADCCmdPreempt;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Starts the requested command buffer processing queue. Valid only
|
||||||
|
* if the SVGA_CAP_HP_CMD_QUEUE cap is set.
|
||||||
|
*
|
||||||
|
* For a command queue to be considered runnable it must be enabled
|
||||||
|
* and any corresponding higher priority queues must also be enabled.
|
||||||
|
* For example in order for command buffers to be processed on
|
||||||
|
* SVGA_CB_CONTEXT_0 both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1 must
|
||||||
|
* be enabled. But for commands to be runnable on SVGA_CB_CONTEXT_1
|
||||||
|
* only that queue must be enabled.
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct SVGADCCmdStartQueue {
|
||||||
|
SVGACBContext context;
|
||||||
|
} SVGADCCmdStartQueue;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Requests the SVGA device to stop processing the requested command
|
||||||
|
* buffer queue as soon as possible. The guest knows the stop has
|
||||||
|
* completed when one of the following happens.
|
||||||
|
*
|
||||||
|
* 1) A command buffer status of SVGA_CB_STATUS_PARTIAL_COMPLETE is returned
|
||||||
|
* 2) A command buffer error is encountered with would stop the queue
|
||||||
|
* regardless of the async stop request.
|
||||||
|
* 3) All command buffers that have been submitted complete successfully.
|
||||||
|
* 4) The stop completes synchronously if no command buffers are
|
||||||
|
* active on the queue when it is issued.
|
||||||
|
*
|
||||||
|
* If the command queue is not in a runnable state there is no
|
||||||
|
* guarentee this async stop will finish. For instance if the high
|
||||||
|
* priority queue is not enabled and a stop is requested on the low
|
||||||
|
* priority queue, the high priority queue must be reenabled to
|
||||||
|
* guarantee that the async stop will finish.
|
||||||
|
*
|
||||||
|
* This command along with SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE can be used
|
||||||
|
* to implement mid command buffer preemption.
|
||||||
|
*
|
||||||
|
* Valid only if the SVGA_CAP_HP_CMD_QUEUE cap is set.
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct SVGADCCmdAsyncStopQueue {
|
||||||
|
SVGACBContext context;
|
||||||
|
} SVGADCCmdAsyncStopQueue;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Requests the SVGA device to throw away any full command buffers on
|
||||||
|
* the requested command queue that have not been started. For a
|
||||||
|
* driver to know which command buffers were thrown away a driver
|
||||||
|
* should only issue this command when the queue is stopped, for
|
||||||
|
* whatever reason.
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct SVGADCCmdEmptyQueue {
|
||||||
|
SVGACBContext context;
|
||||||
|
} SVGADCCmdEmptyQueue;
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SVGAGMRImageFormat --
|
* SVGAGMRImageFormat --
|
||||||
*
|
*
|
||||||
|
@ -537,7 +638,7 @@ typedef struct SVGAGMRImageFormat {
|
||||||
struct {
|
struct {
|
||||||
uint32 bitsPerPixel : 8;
|
uint32 bitsPerPixel : 8;
|
||||||
uint32 colorDepth : 8;
|
uint32 colorDepth : 8;
|
||||||
uint32 reserved : 16; /* Must be zero */
|
uint32 reserved : 16; /* Must be zero */
|
||||||
};
|
};
|
||||||
|
|
||||||
uint32 value;
|
uint32 value;
|
||||||
|
@ -701,6 +802,8 @@ SVGASignedPoint;
|
||||||
* large enough to express any possible topology without holes between
|
* large enough to express any possible topology without holes between
|
||||||
* monitors.)
|
* monitors.)
|
||||||
*
|
*
|
||||||
|
* SVGA_CAP_CAP2_REGISTER --
|
||||||
|
* If this cap is present, the SVGA_REG_CAP2 register is supported.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define SVGA_CAP_NONE 0x00000000
|
#define SVGA_CAP_NONE 0x00000000
|
||||||
|
@ -727,8 +830,29 @@ SVGASignedPoint;
|
||||||
#define SVGA_CAP_DX 0x10000000
|
#define SVGA_CAP_DX 0x10000000
|
||||||
#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
|
#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
|
||||||
#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
|
#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
|
||||||
|
#define SVGA_CAP_CAP2_REGISTER 0x80000000
|
||||||
|
|
||||||
#define SVGA_CAP_CMD_RESERVED 0x80000000
|
/*
|
||||||
|
* The SVGA_REG_CAP2 register is an additional set of SVGA capability bits.
|
||||||
|
*
|
||||||
|
* SVGA_CAP2_GROW_OTABLE --
|
||||||
|
* Allow the GrowOTable/DXGrowCOTable commands.
|
||||||
|
*
|
||||||
|
* SVGA_CAP2_INTRA_SURFACE_COPY --
|
||||||
|
* Allow the IntraSurfaceCopy command.
|
||||||
|
*
|
||||||
|
* SVGA_CAP2_DX2 --
|
||||||
|
* Allow the DefineGBSurface_v3, WholeSurfaceCopy.
|
||||||
|
*
|
||||||
|
* SVGA_CAP2_RESERVED --
|
||||||
|
* Reserve the last bit for extending the SVGA capabilities to some
|
||||||
|
* future mechanisms.
|
||||||
|
*/
|
||||||
|
#define SVGA_CAP2_NONE 0x00000000
|
||||||
|
#define SVGA_CAP2_GROW_OTABLE 0x00000001
|
||||||
|
#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
|
||||||
|
#define SVGA_CAP2_DX2 0x00000004
|
||||||
|
#define SVGA_CAP2_RESERVED 0x80000000
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -750,7 +874,8 @@ typedef enum {
|
||||||
SVGABackdoorCapDeviceCaps = 0,
|
SVGABackdoorCapDeviceCaps = 0,
|
||||||
SVGABackdoorCapFifoCaps = 1,
|
SVGABackdoorCapFifoCaps = 1,
|
||||||
SVGABackdoorCap3dHWVersion = 2,
|
SVGABackdoorCap3dHWVersion = 2,
|
||||||
SVGABackdoorCapMax = 3,
|
SVGABackdoorCapDeviceCaps2 = 3,
|
||||||
|
SVGABackdoorCapMax = 4,
|
||||||
} SVGABackdoorCapType;
|
} SVGABackdoorCapType;
|
||||||
|
|
||||||
|
|
||||||
|
@ -1942,16 +2067,6 @@ SVGAFifoCmdRemapGMR2;
|
||||||
|
|
||||||
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
|
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
|
||||||
|
|
||||||
/*
|
|
||||||
* To simplify autoDetect display configuration, support a minimum of
|
|
||||||
* two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
|
|
||||||
* numDisplays = 2
|
|
||||||
* maxWidth = numDisplay * 1920 = 3840
|
|
||||||
* maxHeight = rotated width of single monitor = 1920
|
|
||||||
* vramSize = maxWidth * maxHeight * 4 = 29491200
|
|
||||||
*/
|
|
||||||
#define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
|
|
||||||
|
|
||||||
#if defined(VMX86_SERVER)
|
#if defined(VMX86_SERVER)
|
||||||
#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
|
#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
|
||||||
#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
|
#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
|
||||||
|
|
|
@ -41,7 +41,10 @@ typedef uint64 PPN64;
|
||||||
|
|
||||||
typedef bool Bool;
|
typedef bool Bool;
|
||||||
|
|
||||||
|
#define MAX_UINT64 U64_MAX
|
||||||
#define MAX_UINT32 U32_MAX
|
#define MAX_UINT32 U32_MAX
|
||||||
#define MAX_UINT16 U16_MAX
|
#define MAX_UINT16 U16_MAX
|
||||||
|
|
||||||
|
#define CONST64U(x) x##ULL
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -137,6 +137,12 @@
|
||||||
#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
|
#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
|
||||||
DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
|
DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
|
||||||
struct drm_vmw_context_arg)
|
struct drm_vmw_context_arg)
|
||||||
|
#define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
|
||||||
|
DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
|
||||||
|
union drm_vmw_gb_surface_create_ext_arg)
|
||||||
|
#define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
|
||||||
|
DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
|
||||||
|
union drm_vmw_gb_surface_reference_ext_arg)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* The core DRM version of this macro doesn't account for
|
* The core DRM version of this macro doesn't account for
|
||||||
|
@ -224,6 +230,12 @@ static const struct drm_ioctl_desc vmw_ioctls[] = {
|
||||||
VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
|
VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
|
||||||
vmw_extended_context_define_ioctl,
|
vmw_extended_context_define_ioctl,
|
||||||
DRM_AUTH | DRM_RENDER_ALLOW),
|
DRM_AUTH | DRM_RENDER_ALLOW),
|
||||||
|
VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
|
||||||
|
vmw_gb_surface_define_ext_ioctl,
|
||||||
|
DRM_AUTH | DRM_RENDER_ALLOW),
|
||||||
|
VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
|
||||||
|
vmw_gb_surface_reference_ext_ioctl,
|
||||||
|
DRM_AUTH | DRM_RENDER_ALLOW),
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct pci_device_id vmw_pci_id_list[] = {
|
static const struct pci_device_id vmw_pci_id_list[] = {
|
||||||
|
@ -258,6 +270,15 @@ MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
|
||||||
module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
|
module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
|
||||||
|
|
||||||
|
|
||||||
|
static void vmw_print_capabilities2(uint32_t capabilities2)
|
||||||
|
{
|
||||||
|
DRM_INFO("Capabilities2:\n");
|
||||||
|
if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
|
||||||
|
DRM_INFO(" Grow oTable.\n");
|
||||||
|
if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
|
||||||
|
DRM_INFO(" IntraSurface copy.\n");
|
||||||
|
}
|
||||||
|
|
||||||
static void vmw_print_capabilities(uint32_t capabilities)
|
static void vmw_print_capabilities(uint32_t capabilities)
|
||||||
{
|
{
|
||||||
DRM_INFO("Capabilities:\n");
|
DRM_INFO("Capabilities:\n");
|
||||||
|
@ -684,6 +705,12 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
|
dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
|
||||||
|
|
||||||
|
if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
|
||||||
|
dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
ret = vmw_dma_select_mode(dev_priv);
|
ret = vmw_dma_select_mode(dev_priv);
|
||||||
if (unlikely(ret != 0)) {
|
if (unlikely(ret != 0)) {
|
||||||
DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
|
DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
|
||||||
|
@ -752,6 +779,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
||||||
}
|
}
|
||||||
|
|
||||||
vmw_print_capabilities(dev_priv->capabilities);
|
vmw_print_capabilities(dev_priv->capabilities);
|
||||||
|
if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
|
||||||
|
vmw_print_capabilities2(dev_priv->capabilities2);
|
||||||
|
|
||||||
ret = vmw_dma_masks(dev_priv);
|
ret = vmw_dma_masks(dev_priv);
|
||||||
if (unlikely(ret != 0))
|
if (unlikely(ret != 0))
|
||||||
|
@ -884,7 +913,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
||||||
|
|
||||||
if (dev_priv->has_mob) {
|
if (dev_priv->has_mob) {
|
||||||
spin_lock(&dev_priv->cap_lock);
|
spin_lock(&dev_priv->cap_lock);
|
||||||
vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
|
||||||
dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
|
dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
|
||||||
spin_unlock(&dev_priv->cap_lock);
|
spin_unlock(&dev_priv->cap_lock);
|
||||||
}
|
}
|
||||||
|
@ -899,9 +928,23 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
||||||
if (ret)
|
if (ret)
|
||||||
goto out_no_fifo;
|
goto out_no_fifo;
|
||||||
|
|
||||||
|
if (dev_priv->has_dx) {
|
||||||
|
/*
|
||||||
|
* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1
|
||||||
|
* support
|
||||||
|
*/
|
||||||
|
if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) {
|
||||||
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP,
|
||||||
|
SVGA3D_DEVCAP_SM41);
|
||||||
|
dev_priv->has_sm4_1 = vmw_read(dev_priv,
|
||||||
|
SVGA_REG_DEV_CAP);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
|
DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
|
||||||
DRM_INFO("Atomic: %s\n",
|
DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
|
||||||
(dev->driver->driver_features & DRIVER_ATOMIC) ? "yes" : "no");
|
? "yes." : "no.");
|
||||||
|
DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no.");
|
||||||
|
|
||||||
snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
|
snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
|
||||||
VMWGFX_REPO, VMWGFX_GIT_VERSION);
|
VMWGFX_REPO, VMWGFX_GIT_VERSION);
|
||||||
|
|
|
@ -43,10 +43,10 @@
|
||||||
#include <linux/sync_file.h>
|
#include <linux/sync_file.h>
|
||||||
|
|
||||||
#define VMWGFX_DRIVER_NAME "vmwgfx"
|
#define VMWGFX_DRIVER_NAME "vmwgfx"
|
||||||
#define VMWGFX_DRIVER_DATE "20180322"
|
#define VMWGFX_DRIVER_DATE "20180704"
|
||||||
#define VMWGFX_DRIVER_MAJOR 2
|
#define VMWGFX_DRIVER_MAJOR 2
|
||||||
#define VMWGFX_DRIVER_MINOR 14
|
#define VMWGFX_DRIVER_MINOR 15
|
||||||
#define VMWGFX_DRIVER_PATCHLEVEL 1
|
#define VMWGFX_DRIVER_PATCHLEVEL 0
|
||||||
#define VMWGFX_FILE_PAGE_OFFSET 0x00100000
|
#define VMWGFX_FILE_PAGE_OFFSET 0x00100000
|
||||||
#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
|
#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
|
||||||
#define VMWGFX_MAX_RELOCATIONS 2048
|
#define VMWGFX_MAX_RELOCATIONS 2048
|
||||||
|
@ -83,7 +83,7 @@
|
||||||
struct vmw_fpriv {
|
struct vmw_fpriv {
|
||||||
struct drm_master *locked_master;
|
struct drm_master *locked_master;
|
||||||
struct ttm_object_file *tfile;
|
struct ttm_object_file *tfile;
|
||||||
bool gb_aware;
|
bool gb_aware; /* user-space is guest-backed aware */
|
||||||
};
|
};
|
||||||
|
|
||||||
struct vmw_buffer_object {
|
struct vmw_buffer_object {
|
||||||
|
@ -166,7 +166,7 @@ struct vmw_surface_offset;
|
||||||
|
|
||||||
struct vmw_surface {
|
struct vmw_surface {
|
||||||
struct vmw_resource res;
|
struct vmw_resource res;
|
||||||
uint32_t flags;
|
SVGA3dSurfaceAllFlags flags;
|
||||||
uint32_t format;
|
uint32_t format;
|
||||||
uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
|
uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
|
||||||
struct drm_vmw_size base_size;
|
struct drm_vmw_size base_size;
|
||||||
|
@ -180,6 +180,8 @@ struct vmw_surface {
|
||||||
SVGA3dTextureFilter autogen_filter;
|
SVGA3dTextureFilter autogen_filter;
|
||||||
uint32_t multisample_count;
|
uint32_t multisample_count;
|
||||||
struct list_head view_list;
|
struct list_head view_list;
|
||||||
|
SVGA3dMSPattern multisample_pattern;
|
||||||
|
SVGA3dMSQualityLevel quality_level;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct vmw_marker_queue {
|
struct vmw_marker_queue {
|
||||||
|
@ -386,6 +388,7 @@ struct vmw_private {
|
||||||
uint32_t initial_height;
|
uint32_t initial_height;
|
||||||
u32 *mmio_virt;
|
u32 *mmio_virt;
|
||||||
uint32_t capabilities;
|
uint32_t capabilities;
|
||||||
|
uint32_t capabilities2;
|
||||||
uint32_t max_gmr_ids;
|
uint32_t max_gmr_ids;
|
||||||
uint32_t max_gmr_pages;
|
uint32_t max_gmr_pages;
|
||||||
uint32_t max_mob_pages;
|
uint32_t max_mob_pages;
|
||||||
|
@ -397,6 +400,7 @@ struct vmw_private {
|
||||||
spinlock_t cap_lock;
|
spinlock_t cap_lock;
|
||||||
bool has_dx;
|
bool has_dx;
|
||||||
bool assume_16bpp;
|
bool assume_16bpp;
|
||||||
|
bool has_sm4_1;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* VGA registers.
|
* VGA registers.
|
||||||
|
@ -1076,14 +1080,22 @@ extern int vmw_surface_validate(struct vmw_private *dev_priv,
|
||||||
struct vmw_surface *srf);
|
struct vmw_surface *srf);
|
||||||
int vmw_surface_gb_priv_define(struct drm_device *dev,
|
int vmw_surface_gb_priv_define(struct drm_device *dev,
|
||||||
uint32_t user_accounting_size,
|
uint32_t user_accounting_size,
|
||||||
uint32_t svga3d_flags,
|
SVGA3dSurfaceAllFlags svga3d_flags,
|
||||||
SVGA3dSurfaceFormat format,
|
SVGA3dSurfaceFormat format,
|
||||||
bool for_scanout,
|
bool for_scanout,
|
||||||
uint32_t num_mip_levels,
|
uint32_t num_mip_levels,
|
||||||
uint32_t multisample_count,
|
uint32_t multisample_count,
|
||||||
uint32_t array_size,
|
uint32_t array_size,
|
||||||
struct drm_vmw_size size,
|
struct drm_vmw_size size,
|
||||||
|
SVGA3dMSPattern multisample_pattern,
|
||||||
|
SVGA3dMSQualityLevel quality_level,
|
||||||
struct vmw_surface **srf_out);
|
struct vmw_surface **srf_out);
|
||||||
|
extern int vmw_gb_surface_define_ext_ioctl(struct drm_device *dev,
|
||||||
|
void *data,
|
||||||
|
struct drm_file *file_priv);
|
||||||
|
extern int vmw_gb_surface_reference_ext_ioctl(struct drm_device *dev,
|
||||||
|
void *data,
|
||||||
|
struct drm_file *file_priv);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Shader management - vmwgfx_shader.c
|
* Shader management - vmwgfx_shader.c
|
||||||
|
|
|
@ -3116,6 +3116,32 @@ static int vmw_cmd_dx_transfer_from_buffer(struct vmw_private *dev_priv,
|
||||||
&cmd->body.destSid, NULL);
|
&cmd->body.destSid, NULL);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vmw_cmd_intra_surface_copy -
|
||||||
|
* Validate an SVGA_3D_CMD_INTRA_SURFACE_COPY command
|
||||||
|
*
|
||||||
|
* @dev_priv: Pointer to a device private struct.
|
||||||
|
* @sw_context: The software context being used for this batch.
|
||||||
|
* @header: Pointer to the command header in the command stream.
|
||||||
|
*/
|
||||||
|
static int vmw_cmd_intra_surface_copy(struct vmw_private *dev_priv,
|
||||||
|
struct vmw_sw_context *sw_context,
|
||||||
|
SVGA3dCmdHeader *header)
|
||||||
|
{
|
||||||
|
struct {
|
||||||
|
SVGA3dCmdHeader header;
|
||||||
|
SVGA3dCmdIntraSurfaceCopy body;
|
||||||
|
} *cmd = container_of(header, typeof(*cmd), header);
|
||||||
|
|
||||||
|
if (!(dev_priv->capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
|
||||||
|
user_surface_converter,
|
||||||
|
&cmd->body.surface.sid, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
|
static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
|
||||||
struct vmw_sw_context *sw_context,
|
struct vmw_sw_context *sw_context,
|
||||||
void *buf, uint32_t *size)
|
void *buf, uint32_t *size)
|
||||||
|
@ -3230,9 +3256,9 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
|
||||||
false, false, false),
|
false, false, false),
|
||||||
VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid,
|
VMW_CMD_DEF(SVGA_3D_CMD_SCREEN_DMA, &vmw_cmd_invalid,
|
||||||
false, false, false),
|
false, false, false),
|
||||||
VMW_CMD_DEF(SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE, &vmw_cmd_invalid,
|
VMW_CMD_DEF(SVGA_3D_CMD_DEAD1, &vmw_cmd_invalid,
|
||||||
false, false, false),
|
false, false, false),
|
||||||
VMW_CMD_DEF(SVGA_3D_CMD_OPEN_CONTEXT_SURFACE, &vmw_cmd_invalid,
|
VMW_CMD_DEF(SVGA_3D_CMD_DEAD2, &vmw_cmd_invalid,
|
||||||
false, false, false),
|
false, false, false),
|
||||||
VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_BITBLT, &vmw_cmd_invalid,
|
VMW_CMD_DEF(SVGA_3D_CMD_LOGICOPS_BITBLT, &vmw_cmd_invalid,
|
||||||
false, false, false),
|
false, false, false),
|
||||||
|
@ -3471,6 +3497,8 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
|
||||||
VMW_CMD_DEF(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER,
|
VMW_CMD_DEF(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER,
|
||||||
&vmw_cmd_dx_transfer_from_buffer,
|
&vmw_cmd_dx_transfer_from_buffer,
|
||||||
true, false, true),
|
true, false, true),
|
||||||
|
VMW_CMD_DEF(SVGA_3D_CMD_INTRA_SURFACE_COPY, &vmw_cmd_intra_surface_copy,
|
||||||
|
true, false, true),
|
||||||
};
|
};
|
||||||
|
|
||||||
bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd)
|
bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd)
|
||||||
|
|
|
@ -56,6 +56,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
|
||||||
case DRM_VMW_PARAM_HW_CAPS:
|
case DRM_VMW_PARAM_HW_CAPS:
|
||||||
param->value = dev_priv->capabilities;
|
param->value = dev_priv->capabilities;
|
||||||
break;
|
break;
|
||||||
|
case DRM_VMW_PARAM_HW_CAPS2:
|
||||||
|
param->value = dev_priv->capabilities2;
|
||||||
|
break;
|
||||||
case DRM_VMW_PARAM_FIFO_CAPS:
|
case DRM_VMW_PARAM_FIFO_CAPS:
|
||||||
param->value = dev_priv->fifo.capabilities;
|
param->value = dev_priv->fifo.capabilities;
|
||||||
break;
|
break;
|
||||||
|
@ -113,6 +116,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
|
||||||
case DRM_VMW_PARAM_DX:
|
case DRM_VMW_PARAM_DX:
|
||||||
param->value = dev_priv->has_dx;
|
param->value = dev_priv->has_dx;
|
||||||
break;
|
break;
|
||||||
|
case DRM_VMW_PARAM_SM4_1:
|
||||||
|
param->value = dev_priv->has_sm4_1;
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
@ -122,15 +128,12 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
|
||||||
|
|
||||||
static u32 vmw_mask_multisample(unsigned int cap, u32 fmt_value)
|
static u32 vmw_mask_multisample(unsigned int cap, u32 fmt_value)
|
||||||
{
|
{
|
||||||
/* If the header is updated, update the format test as well! */
|
/*
|
||||||
BUILD_BUG_ON(SVGA3D_DEVCAP_DXFMT_BC5_UNORM + 1 != SVGA3D_DEVCAP_MAX);
|
* A version of user-space exists which use MULTISAMPLE_MASKABLESAMPLES
|
||||||
|
* to check the sample count supported by virtual device. Since there
|
||||||
if (cap >= SVGA3D_DEVCAP_DXFMT_X8R8G8B8 &&
|
* never was support for multisample count for backing MOB return 0.
|
||||||
cap <= SVGA3D_DEVCAP_DXFMT_BC5_UNORM)
|
*/
|
||||||
fmt_value &= ~(SVGADX_DXFMT_MULTISAMPLE_2 |
|
if (cap == SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES)
|
||||||
SVGADX_DXFMT_MULTISAMPLE_4 |
|
|
||||||
SVGADX_DXFMT_MULTISAMPLE_8);
|
|
||||||
else if (cap == SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES)
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
return fmt_value;
|
return fmt_value;
|
||||||
|
|
|
@ -1238,15 +1238,17 @@ static int vmw_create_bo_proxy(struct drm_device *dev,
|
||||||
content_base_size.depth = 1;
|
content_base_size.depth = 1;
|
||||||
|
|
||||||
ret = vmw_surface_gb_priv_define(dev,
|
ret = vmw_surface_gb_priv_define(dev,
|
||||||
0, /* kernel visible only */
|
0, /* kernel visible only */
|
||||||
0, /* flags */
|
0, /* flags */
|
||||||
format,
|
format,
|
||||||
true, /* can be a scanout buffer */
|
true, /* can be a scanout buffer */
|
||||||
1, /* num of mip levels */
|
1, /* num of mip levels */
|
||||||
0,
|
0,
|
||||||
0,
|
0,
|
||||||
content_base_size,
|
content_base_size,
|
||||||
srf_out);
|
SVGA3D_MS_PATTERN_NONE,
|
||||||
|
SVGA3D_MS_QUALITY_NONE,
|
||||||
|
srf_out);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
DRM_ERROR("Failed to allocate proxy content buffer\n");
|
DRM_ERROR("Failed to allocate proxy content buffer\n");
|
||||||
return ret;
|
return ret;
|
||||||
|
|
|
@ -1157,6 +1157,9 @@ vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane,
|
||||||
content_srf.flags = 0;
|
content_srf.flags = 0;
|
||||||
content_srf.mip_levels[0] = 1;
|
content_srf.mip_levels[0] = 1;
|
||||||
content_srf.multisample_count = 0;
|
content_srf.multisample_count = 0;
|
||||||
|
content_srf.multisample_pattern =
|
||||||
|
SVGA3D_MS_PATTERN_NONE;
|
||||||
|
content_srf.quality_level = SVGA3D_MS_QUALITY_NONE;
|
||||||
} else {
|
} else {
|
||||||
content_srf = *new_vfbs->surface;
|
content_srf = *new_vfbs->surface;
|
||||||
}
|
}
|
||||||
|
@ -1185,6 +1188,8 @@ vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane,
|
||||||
content_srf.multisample_count,
|
content_srf.multisample_count,
|
||||||
0,
|
0,
|
||||||
display_base_size,
|
display_base_size,
|
||||||
|
content_srf.multisample_pattern,
|
||||||
|
content_srf.quality_level,
|
||||||
&vps->surf);
|
&vps->surf);
|
||||||
if (ret != 0) {
|
if (ret != 0) {
|
||||||
DRM_ERROR("Couldn't allocate STDU surface.\n");
|
DRM_ERROR("Couldn't allocate STDU surface.\n");
|
||||||
|
|
|
@ -33,6 +33,10 @@
|
||||||
#include "vmwgfx_binding.h"
|
#include "vmwgfx_binding.h"
|
||||||
#include "device_include/svga3d_surfacedefs.h"
|
#include "device_include/svga3d_surfacedefs.h"
|
||||||
|
|
||||||
|
#define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
|
||||||
|
#define SVGA3D_FLAGS_UPPER_32(svga3d_flags) (svga3d_flags >> 32)
|
||||||
|
#define SVGA3D_FLAGS_LOWER_32(svga3d_flags) \
|
||||||
|
(svga3d_flags & ((uint64_t)U32_MAX))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct vmw_user_surface - User-space visible surface resource
|
* struct vmw_user_surface - User-space visible surface resource
|
||||||
|
@ -81,7 +85,16 @@ static int vmw_gb_surface_unbind(struct vmw_resource *res,
|
||||||
bool readback,
|
bool readback,
|
||||||
struct ttm_validate_buffer *val_buf);
|
struct ttm_validate_buffer *val_buf);
|
||||||
static int vmw_gb_surface_destroy(struct vmw_resource *res);
|
static int vmw_gb_surface_destroy(struct vmw_resource *res);
|
||||||
|
static int
|
||||||
|
vmw_gb_surface_define_internal(struct drm_device *dev,
|
||||||
|
struct drm_vmw_gb_surface_create_ext_req *req,
|
||||||
|
struct drm_vmw_gb_surface_create_rep *rep,
|
||||||
|
struct drm_file *file_priv);
|
||||||
|
static int
|
||||||
|
vmw_gb_surface_reference_internal(struct drm_device *dev,
|
||||||
|
struct drm_vmw_surface_arg *req,
|
||||||
|
struct drm_vmw_gb_surface_ref_ext_rep *rep,
|
||||||
|
struct drm_file *file_priv);
|
||||||
|
|
||||||
static const struct vmw_user_resource_conv user_surface_conv = {
|
static const struct vmw_user_resource_conv user_surface_conv = {
|
||||||
.object_type = VMW_RES_SURFACE,
|
.object_type = VMW_RES_SURFACE,
|
||||||
|
@ -224,7 +237,12 @@ static void vmw_surface_define_encode(const struct vmw_surface *srf,
|
||||||
cmd->header.id = SVGA_3D_CMD_SURFACE_DEFINE;
|
cmd->header.id = SVGA_3D_CMD_SURFACE_DEFINE;
|
||||||
cmd->header.size = cmd_len;
|
cmd->header.size = cmd_len;
|
||||||
cmd->body.sid = srf->res.id;
|
cmd->body.sid = srf->res.id;
|
||||||
cmd->body.surfaceFlags = srf->flags;
|
/*
|
||||||
|
* Downcast of surfaceFlags, was upcasted when received from user-space,
|
||||||
|
* since driver internally stores as 64 bit.
|
||||||
|
* For legacy surface define only 32 bit flag is supported.
|
||||||
|
*/
|
||||||
|
cmd->body.surfaceFlags = (SVGA3dSurface1Flags)srf->flags;
|
||||||
cmd->body.format = srf->format;
|
cmd->body.format = srf->format;
|
||||||
for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i)
|
for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i)
|
||||||
cmd->body.face[i].numMipLevels = srf->mip_levels[i];
|
cmd->body.face[i].numMipLevels = srf->mip_levels[i];
|
||||||
|
@ -760,7 +778,8 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
|
||||||
srf = &user_srf->srf;
|
srf = &user_srf->srf;
|
||||||
res = &srf->res;
|
res = &srf->res;
|
||||||
|
|
||||||
srf->flags = req->flags;
|
/* Driver internally stores as 64-bit flags */
|
||||||
|
srf->flags = (SVGA3dSurfaceAllFlags)req->flags;
|
||||||
srf->format = req->format;
|
srf->format = req->format;
|
||||||
srf->scanout = req->scanout;
|
srf->scanout = req->scanout;
|
||||||
|
|
||||||
|
@ -785,6 +804,8 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
|
||||||
srf->base_size = *srf->sizes;
|
srf->base_size = *srf->sizes;
|
||||||
srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
|
srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
|
||||||
srf->multisample_count = 0;
|
srf->multisample_count = 0;
|
||||||
|
srf->multisample_pattern = SVGA3D_MS_PATTERN_NONE;
|
||||||
|
srf->quality_level = SVGA3D_MS_QUALITY_NONE;
|
||||||
|
|
||||||
cur_bo_offset = 0;
|
cur_bo_offset = 0;
|
||||||
cur_offset = srf->offsets;
|
cur_offset = srf->offsets;
|
||||||
|
@ -990,7 +1011,8 @@ int vmw_surface_reference_ioctl(struct drm_device *dev, void *data,
|
||||||
user_srf = container_of(base, struct vmw_user_surface, prime.base);
|
user_srf = container_of(base, struct vmw_user_surface, prime.base);
|
||||||
srf = &user_srf->srf;
|
srf = &user_srf->srf;
|
||||||
|
|
||||||
rep->flags = srf->flags;
|
/* Downcast of flags when sending back to user space */
|
||||||
|
rep->flags = (uint32_t)srf->flags;
|
||||||
rep->format = srf->format;
|
rep->format = srf->format;
|
||||||
memcpy(rep->mip_levels, srf->mip_levels, sizeof(srf->mip_levels));
|
memcpy(rep->mip_levels, srf->mip_levels, sizeof(srf->mip_levels));
|
||||||
user_sizes = (struct drm_vmw_size __user *)(unsigned long)
|
user_sizes = (struct drm_vmw_size __user *)(unsigned long)
|
||||||
|
@ -1031,6 +1053,10 @@ static int vmw_gb_surface_create(struct vmw_resource *res)
|
||||||
SVGA3dCmdHeader header;
|
SVGA3dCmdHeader header;
|
||||||
SVGA3dCmdDefineGBSurface_v2 body;
|
SVGA3dCmdDefineGBSurface_v2 body;
|
||||||
} *cmd2;
|
} *cmd2;
|
||||||
|
struct {
|
||||||
|
SVGA3dCmdHeader header;
|
||||||
|
SVGA3dCmdDefineGBSurface_v3 body;
|
||||||
|
} *cmd3;
|
||||||
|
|
||||||
if (likely(res->id != -1))
|
if (likely(res->id != -1))
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -1047,7 +1073,11 @@ static int vmw_gb_surface_create(struct vmw_resource *res)
|
||||||
goto out_no_fifo;
|
goto out_no_fifo;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (srf->array_size > 0) {
|
if (dev_priv->has_sm4_1 && srf->array_size > 0) {
|
||||||
|
cmd_id = SVGA_3D_CMD_DEFINE_GB_SURFACE_V3;
|
||||||
|
cmd_len = sizeof(cmd3->body);
|
||||||
|
submit_len = sizeof(*cmd3);
|
||||||
|
} else if (srf->array_size > 0) {
|
||||||
/* has_dx checked on creation time. */
|
/* has_dx checked on creation time. */
|
||||||
cmd_id = SVGA_3D_CMD_DEFINE_GB_SURFACE_V2;
|
cmd_id = SVGA_3D_CMD_DEFINE_GB_SURFACE_V2;
|
||||||
cmd_len = sizeof(cmd2->body);
|
cmd_len = sizeof(cmd2->body);
|
||||||
|
@ -1060,6 +1090,7 @@ static int vmw_gb_surface_create(struct vmw_resource *res)
|
||||||
|
|
||||||
cmd = vmw_fifo_reserve(dev_priv, submit_len);
|
cmd = vmw_fifo_reserve(dev_priv, submit_len);
|
||||||
cmd2 = (typeof(cmd2))cmd;
|
cmd2 = (typeof(cmd2))cmd;
|
||||||
|
cmd3 = (typeof(cmd3))cmd;
|
||||||
if (unlikely(!cmd)) {
|
if (unlikely(!cmd)) {
|
||||||
DRM_ERROR("Failed reserving FIFO space for surface "
|
DRM_ERROR("Failed reserving FIFO space for surface "
|
||||||
"creation.\n");
|
"creation.\n");
|
||||||
|
@ -1067,7 +1098,22 @@ static int vmw_gb_surface_create(struct vmw_resource *res)
|
||||||
goto out_no_fifo;
|
goto out_no_fifo;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (srf->array_size > 0) {
|
if (dev_priv->has_sm4_1 && srf->array_size > 0) {
|
||||||
|
cmd3->header.id = cmd_id;
|
||||||
|
cmd3->header.size = cmd_len;
|
||||||
|
cmd3->body.sid = srf->res.id;
|
||||||
|
cmd3->body.surfaceFlags = srf->flags;
|
||||||
|
cmd3->body.format = srf->format;
|
||||||
|
cmd3->body.numMipLevels = srf->mip_levels[0];
|
||||||
|
cmd3->body.multisampleCount = srf->multisample_count;
|
||||||
|
cmd3->body.multisamplePattern = srf->multisample_pattern;
|
||||||
|
cmd3->body.qualityLevel = srf->quality_level;
|
||||||
|
cmd3->body.autogenFilter = srf->autogen_filter;
|
||||||
|
cmd3->body.size.width = srf->base_size.width;
|
||||||
|
cmd3->body.size.height = srf->base_size.height;
|
||||||
|
cmd3->body.size.depth = srf->base_size.depth;
|
||||||
|
cmd3->body.arraySize = srf->array_size;
|
||||||
|
} else if (srf->array_size > 0) {
|
||||||
cmd2->header.id = cmd_id;
|
cmd2->header.id = cmd_id;
|
||||||
cmd2->header.size = cmd_len;
|
cmd2->header.size = cmd_len;
|
||||||
cmd2->body.sid = srf->res.id;
|
cmd2->body.sid = srf->res.id;
|
||||||
|
@ -1256,193 +1302,55 @@ static int vmw_gb_surface_destroy(struct vmw_resource *res)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vmw_gb_surface_define_ioctl - Ioctl function implementing
|
* vmw_gb_surface_define_ioctl - Ioctl function implementing
|
||||||
* the user surface define functionality.
|
* the user surface define functionality.
|
||||||
*
|
*
|
||||||
* @dev: Pointer to a struct drm_device.
|
* @dev: Pointer to a struct drm_device.
|
||||||
* @data: Pointer to data copied from / to user-space.
|
* @data: Pointer to data copied from / to user-space.
|
||||||
* @file_priv: Pointer to a drm file private structure.
|
* @file_priv: Pointer to a drm file private structure.
|
||||||
*/
|
*/
|
||||||
int vmw_gb_surface_define_ioctl(struct drm_device *dev, void *data,
|
int vmw_gb_surface_define_ioctl(struct drm_device *dev, void *data,
|
||||||
struct drm_file *file_priv)
|
struct drm_file *file_priv)
|
||||||
{
|
{
|
||||||
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
||||||
struct vmw_user_surface *user_srf;
|
|
||||||
struct vmw_surface *srf;
|
|
||||||
struct vmw_resource *res;
|
|
||||||
struct vmw_resource *tmp;
|
|
||||||
union drm_vmw_gb_surface_create_arg *arg =
|
union drm_vmw_gb_surface_create_arg *arg =
|
||||||
(union drm_vmw_gb_surface_create_arg *)data;
|
(union drm_vmw_gb_surface_create_arg *)data;
|
||||||
struct drm_vmw_gb_surface_create_req *req = &arg->req;
|
|
||||||
struct drm_vmw_gb_surface_create_rep *rep = &arg->rep;
|
struct drm_vmw_gb_surface_create_rep *rep = &arg->rep;
|
||||||
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
|
struct drm_vmw_gb_surface_create_ext_req req_ext;
|
||||||
int ret;
|
|
||||||
uint32_t size;
|
|
||||||
uint32_t backup_handle = 0;
|
|
||||||
|
|
||||||
if (req->multisample_count != 0)
|
req_ext.base = arg->req;
|
||||||
return -EINVAL;
|
req_ext.version = drm_vmw_gb_surface_v1;
|
||||||
|
req_ext.svga3d_flags_upper_32_bits = 0;
|
||||||
|
req_ext.multisample_pattern = SVGA3D_MS_PATTERN_NONE;
|
||||||
|
req_ext.quality_level = SVGA3D_MS_QUALITY_NONE;
|
||||||
|
req_ext.must_be_zero = 0;
|
||||||
|
|
||||||
if (req->mip_levels > DRM_VMW_MAX_MIP_LEVELS)
|
return vmw_gb_surface_define_internal(dev, &req_ext, rep, file_priv);
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
if (unlikely(vmw_user_surface_size == 0))
|
|
||||||
vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
|
|
||||||
128;
|
|
||||||
|
|
||||||
size = vmw_user_surface_size + 128;
|
|
||||||
|
|
||||||
/* Define a surface based on the parameters. */
|
|
||||||
ret = vmw_surface_gb_priv_define(dev,
|
|
||||||
size,
|
|
||||||
req->svga3d_flags,
|
|
||||||
req->format,
|
|
||||||
req->drm_surface_flags & drm_vmw_surface_flag_scanout,
|
|
||||||
req->mip_levels,
|
|
||||||
req->multisample_count,
|
|
||||||
req->array_size,
|
|
||||||
req->base_size,
|
|
||||||
&srf);
|
|
||||||
if (unlikely(ret != 0))
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
user_srf = container_of(srf, struct vmw_user_surface, srf);
|
|
||||||
if (drm_is_primary_client(file_priv))
|
|
||||||
user_srf->master = drm_master_get(file_priv->master);
|
|
||||||
|
|
||||||
ret = ttm_read_lock(&dev_priv->reservation_sem, true);
|
|
||||||
if (unlikely(ret != 0))
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
res = &user_srf->srf.res;
|
|
||||||
|
|
||||||
|
|
||||||
if (req->buffer_handle != SVGA3D_INVALID_ID) {
|
|
||||||
ret = vmw_user_bo_lookup(tfile, req->buffer_handle,
|
|
||||||
&res->backup,
|
|
||||||
&user_srf->backup_base);
|
|
||||||
if (ret == 0) {
|
|
||||||
if (res->backup->base.num_pages * PAGE_SIZE <
|
|
||||||
res->backup_size) {
|
|
||||||
DRM_ERROR("Surface backup buffer is too small.\n");
|
|
||||||
vmw_bo_unreference(&res->backup);
|
|
||||||
ret = -EINVAL;
|
|
||||||
goto out_unlock;
|
|
||||||
} else {
|
|
||||||
backup_handle = req->buffer_handle;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else if (req->drm_surface_flags & drm_vmw_surface_flag_create_buffer)
|
|
||||||
ret = vmw_user_bo_alloc(dev_priv, tfile,
|
|
||||||
res->backup_size,
|
|
||||||
req->drm_surface_flags &
|
|
||||||
drm_vmw_surface_flag_shareable,
|
|
||||||
&backup_handle,
|
|
||||||
&res->backup,
|
|
||||||
&user_srf->backup_base);
|
|
||||||
|
|
||||||
if (unlikely(ret != 0)) {
|
|
||||||
vmw_resource_unreference(&res);
|
|
||||||
goto out_unlock;
|
|
||||||
}
|
|
||||||
|
|
||||||
tmp = vmw_resource_reference(res);
|
|
||||||
ret = ttm_prime_object_init(tfile, res->backup_size, &user_srf->prime,
|
|
||||||
req->drm_surface_flags &
|
|
||||||
drm_vmw_surface_flag_shareable,
|
|
||||||
VMW_RES_SURFACE,
|
|
||||||
&vmw_user_surface_base_release, NULL);
|
|
||||||
|
|
||||||
if (unlikely(ret != 0)) {
|
|
||||||
vmw_resource_unreference(&tmp);
|
|
||||||
vmw_resource_unreference(&res);
|
|
||||||
goto out_unlock;
|
|
||||||
}
|
|
||||||
|
|
||||||
rep->handle = user_srf->prime.base.hash.key;
|
|
||||||
rep->backup_size = res->backup_size;
|
|
||||||
if (res->backup) {
|
|
||||||
rep->buffer_map_handle =
|
|
||||||
drm_vma_node_offset_addr(&res->backup->base.vma_node);
|
|
||||||
rep->buffer_size = res->backup->base.num_pages * PAGE_SIZE;
|
|
||||||
rep->buffer_handle = backup_handle;
|
|
||||||
} else {
|
|
||||||
rep->buffer_map_handle = 0;
|
|
||||||
rep->buffer_size = 0;
|
|
||||||
rep->buffer_handle = SVGA3D_INVALID_ID;
|
|
||||||
}
|
|
||||||
|
|
||||||
vmw_resource_unreference(&res);
|
|
||||||
|
|
||||||
out_unlock:
|
|
||||||
ttm_read_unlock(&dev_priv->reservation_sem);
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vmw_gb_surface_reference_ioctl - Ioctl function implementing
|
* vmw_gb_surface_reference_ioctl - Ioctl function implementing
|
||||||
* the user surface reference functionality.
|
* the user surface reference functionality.
|
||||||
*
|
*
|
||||||
* @dev: Pointer to a struct drm_device.
|
* @dev: Pointer to a struct drm_device.
|
||||||
* @data: Pointer to data copied from / to user-space.
|
* @data: Pointer to data copied from / to user-space.
|
||||||
* @file_priv: Pointer to a drm file private structure.
|
* @file_priv: Pointer to a drm file private structure.
|
||||||
*/
|
*/
|
||||||
int vmw_gb_surface_reference_ioctl(struct drm_device *dev, void *data,
|
int vmw_gb_surface_reference_ioctl(struct drm_device *dev, void *data,
|
||||||
struct drm_file *file_priv)
|
struct drm_file *file_priv)
|
||||||
{
|
{
|
||||||
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
||||||
union drm_vmw_gb_surface_reference_arg *arg =
|
union drm_vmw_gb_surface_reference_arg *arg =
|
||||||
(union drm_vmw_gb_surface_reference_arg *)data;
|
(union drm_vmw_gb_surface_reference_arg *)data;
|
||||||
struct drm_vmw_surface_arg *req = &arg->req;
|
struct drm_vmw_surface_arg *req = &arg->req;
|
||||||
struct drm_vmw_gb_surface_ref_rep *rep = &arg->rep;
|
struct drm_vmw_gb_surface_ref_rep *rep = &arg->rep;
|
||||||
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
|
struct drm_vmw_gb_surface_ref_ext_rep rep_ext;
|
||||||
struct vmw_surface *srf;
|
int ret;
|
||||||
struct vmw_user_surface *user_srf;
|
|
||||||
struct ttm_base_object *base;
|
ret = vmw_gb_surface_reference_internal(dev, req, &rep_ext, file_priv);
|
||||||
uint32_t backup_handle;
|
|
||||||
int ret = -EINVAL;
|
|
||||||
|
|
||||||
ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid,
|
|
||||||
req->handle_type, &base);
|
|
||||||
if (unlikely(ret != 0))
|
if (unlikely(ret != 0))
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
user_srf = container_of(base, struct vmw_user_surface, prime.base);
|
rep->creq = rep_ext.creq.base;
|
||||||
srf = &user_srf->srf;
|
rep->crep = rep_ext.crep;
|
||||||
if (!srf->res.backup) {
|
|
||||||
DRM_ERROR("Shared GB surface is missing a backup buffer.\n");
|
|
||||||
goto out_bad_resource;
|
|
||||||
}
|
|
||||||
|
|
||||||
mutex_lock(&dev_priv->cmdbuf_mutex); /* Protect res->backup */
|
|
||||||
ret = vmw_user_bo_reference(tfile, srf->res.backup, &backup_handle);
|
|
||||||
mutex_unlock(&dev_priv->cmdbuf_mutex);
|
|
||||||
|
|
||||||
if (unlikely(ret != 0)) {
|
|
||||||
DRM_ERROR("Could not add a reference to a GB surface "
|
|
||||||
"backup buffer.\n");
|
|
||||||
(void) ttm_ref_object_base_unref(tfile, base->hash.key,
|
|
||||||
TTM_REF_USAGE);
|
|
||||||
goto out_bad_resource;
|
|
||||||
}
|
|
||||||
|
|
||||||
rep->creq.svga3d_flags = srf->flags;
|
|
||||||
rep->creq.format = srf->format;
|
|
||||||
rep->creq.mip_levels = srf->mip_levels[0];
|
|
||||||
rep->creq.drm_surface_flags = 0;
|
|
||||||
rep->creq.multisample_count = srf->multisample_count;
|
|
||||||
rep->creq.autogen_filter = srf->autogen_filter;
|
|
||||||
rep->creq.array_size = srf->array_size;
|
|
||||||
rep->creq.buffer_handle = backup_handle;
|
|
||||||
rep->creq.base_size = srf->base_size;
|
|
||||||
rep->crep.handle = user_srf->prime.base.hash.key;
|
|
||||||
rep->crep.backup_size = srf->res.backup_size;
|
|
||||||
rep->crep.buffer_handle = backup_handle;
|
|
||||||
rep->crep.buffer_map_handle =
|
|
||||||
drm_vma_node_offset_addr(&srf->res.backup->base.vma_node);
|
|
||||||
rep->crep.buffer_size = srf->res.backup->base.num_pages * PAGE_SIZE;
|
|
||||||
|
|
||||||
out_bad_resource:
|
|
||||||
ttm_base_object_unref(&base);
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -1460,6 +1368,8 @@ int vmw_gb_surface_reference_ioctl(struct drm_device *dev, void *data,
|
||||||
* @multisample_count:
|
* @multisample_count:
|
||||||
* @array_size: Surface array size.
|
* @array_size: Surface array size.
|
||||||
* @size: width, heigh, depth of the surface requested
|
* @size: width, heigh, depth of the surface requested
|
||||||
|
* @multisample_pattern: Multisampling pattern when msaa is supported
|
||||||
|
* @quality_level: Precision settings
|
||||||
* @user_srf_out: allocated user_srf. Set to NULL on failure.
|
* @user_srf_out: allocated user_srf. Set to NULL on failure.
|
||||||
*
|
*
|
||||||
* GB surfaces allocated by this function will not have a user mode handle, and
|
* GB surfaces allocated by this function will not have a user mode handle, and
|
||||||
|
@ -1469,13 +1379,15 @@ int vmw_gb_surface_reference_ioctl(struct drm_device *dev, void *data,
|
||||||
*/
|
*/
|
||||||
int vmw_surface_gb_priv_define(struct drm_device *dev,
|
int vmw_surface_gb_priv_define(struct drm_device *dev,
|
||||||
uint32_t user_accounting_size,
|
uint32_t user_accounting_size,
|
||||||
uint32_t svga3d_flags,
|
SVGA3dSurfaceAllFlags svga3d_flags,
|
||||||
SVGA3dSurfaceFormat format,
|
SVGA3dSurfaceFormat format,
|
||||||
bool for_scanout,
|
bool for_scanout,
|
||||||
uint32_t num_mip_levels,
|
uint32_t num_mip_levels,
|
||||||
uint32_t multisample_count,
|
uint32_t multisample_count,
|
||||||
uint32_t array_size,
|
uint32_t array_size,
|
||||||
struct drm_vmw_size size,
|
struct drm_vmw_size size,
|
||||||
|
SVGA3dMSPattern multisample_pattern,
|
||||||
|
SVGA3dMSQualityLevel quality_level,
|
||||||
struct vmw_surface **srf_out)
|
struct vmw_surface **srf_out)
|
||||||
{
|
{
|
||||||
struct vmw_private *dev_priv = vmw_priv(dev);
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
||||||
|
@ -1486,7 +1398,8 @@ int vmw_surface_gb_priv_define(struct drm_device *dev,
|
||||||
};
|
};
|
||||||
struct vmw_surface *srf;
|
struct vmw_surface *srf;
|
||||||
int ret;
|
int ret;
|
||||||
u32 num_layers;
|
u32 num_layers = 1;
|
||||||
|
u32 sample_count = 1;
|
||||||
|
|
||||||
*srf_out = NULL;
|
*srf_out = NULL;
|
||||||
|
|
||||||
|
@ -1561,19 +1474,23 @@ int vmw_surface_gb_priv_define(struct drm_device *dev,
|
||||||
srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
|
srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
|
||||||
srf->array_size = array_size;
|
srf->array_size = array_size;
|
||||||
srf->multisample_count = multisample_count;
|
srf->multisample_count = multisample_count;
|
||||||
|
srf->multisample_pattern = multisample_pattern;
|
||||||
|
srf->quality_level = quality_level;
|
||||||
|
|
||||||
if (array_size)
|
if (array_size)
|
||||||
num_layers = array_size;
|
num_layers = array_size;
|
||||||
else if (svga3d_flags & SVGA3D_SURFACE_CUBEMAP)
|
else if (svga3d_flags & SVGA3D_SURFACE_CUBEMAP)
|
||||||
num_layers = SVGA3D_MAX_SURFACE_FACES;
|
num_layers = SVGA3D_MAX_SURFACE_FACES;
|
||||||
else
|
|
||||||
num_layers = 1;
|
if (srf->flags & SVGA3D_SURFACE_MULTISAMPLE)
|
||||||
|
sample_count = srf->multisample_count;
|
||||||
|
|
||||||
srf->res.backup_size =
|
srf->res.backup_size =
|
||||||
svga3dsurface_get_serialized_size(srf->format,
|
svga3dsurface_get_serialized_size_extended(srf->format,
|
||||||
srf->base_size,
|
srf->base_size,
|
||||||
srf->mip_levels[0],
|
srf->mip_levels[0],
|
||||||
num_layers);
|
num_layers,
|
||||||
|
sample_count);
|
||||||
|
|
||||||
if (srf->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
|
if (srf->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
|
||||||
srf->res.backup_size += sizeof(SVGA3dDXSOState);
|
srf->res.backup_size += sizeof(SVGA3dDXSOState);
|
||||||
|
@ -1598,3 +1515,266 @@ int vmw_surface_gb_priv_define(struct drm_device *dev,
|
||||||
ttm_read_unlock(&dev_priv->reservation_sem);
|
ttm_read_unlock(&dev_priv->reservation_sem);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vmw_gb_surface_define_ext_ioctl - Ioctl function implementing
|
||||||
|
* the user surface define functionality.
|
||||||
|
*
|
||||||
|
* @dev: Pointer to a struct drm_device.
|
||||||
|
* @data: Pointer to data copied from / to user-space.
|
||||||
|
* @file_priv: Pointer to a drm file private structure.
|
||||||
|
*/
|
||||||
|
int vmw_gb_surface_define_ext_ioctl(struct drm_device *dev, void *data,
|
||||||
|
struct drm_file *file_priv)
|
||||||
|
{
|
||||||
|
union drm_vmw_gb_surface_create_ext_arg *arg =
|
||||||
|
(union drm_vmw_gb_surface_create_ext_arg *)data;
|
||||||
|
struct drm_vmw_gb_surface_create_ext_req *req = &arg->req;
|
||||||
|
struct drm_vmw_gb_surface_create_rep *rep = &arg->rep;
|
||||||
|
|
||||||
|
return vmw_gb_surface_define_internal(dev, req, rep, file_priv);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vmw_gb_surface_reference_ext_ioctl - Ioctl function implementing
|
||||||
|
* the user surface reference functionality.
|
||||||
|
*
|
||||||
|
* @dev: Pointer to a struct drm_device.
|
||||||
|
* @data: Pointer to data copied from / to user-space.
|
||||||
|
* @file_priv: Pointer to a drm file private structure.
|
||||||
|
*/
|
||||||
|
int vmw_gb_surface_reference_ext_ioctl(struct drm_device *dev, void *data,
|
||||||
|
struct drm_file *file_priv)
|
||||||
|
{
|
||||||
|
union drm_vmw_gb_surface_reference_ext_arg *arg =
|
||||||
|
(union drm_vmw_gb_surface_reference_ext_arg *)data;
|
||||||
|
struct drm_vmw_surface_arg *req = &arg->req;
|
||||||
|
struct drm_vmw_gb_surface_ref_ext_rep *rep = &arg->rep;
|
||||||
|
|
||||||
|
return vmw_gb_surface_reference_internal(dev, req, rep, file_priv);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vmw_gb_surface_define_internal - Ioctl function implementing
|
||||||
|
* the user surface define functionality.
|
||||||
|
*
|
||||||
|
* @dev: Pointer to a struct drm_device.
|
||||||
|
* @req: Request argument from user-space.
|
||||||
|
* @rep: Response argument to user-space.
|
||||||
|
* @file_priv: Pointer to a drm file private structure.
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
vmw_gb_surface_define_internal(struct drm_device *dev,
|
||||||
|
struct drm_vmw_gb_surface_create_ext_req *req,
|
||||||
|
struct drm_vmw_gb_surface_create_rep *rep,
|
||||||
|
struct drm_file *file_priv)
|
||||||
|
{
|
||||||
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
||||||
|
struct vmw_user_surface *user_srf;
|
||||||
|
struct vmw_surface *srf;
|
||||||
|
struct vmw_resource *res;
|
||||||
|
struct vmw_resource *tmp;
|
||||||
|
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
|
||||||
|
int ret;
|
||||||
|
uint32_t size;
|
||||||
|
uint32_t backup_handle = 0;
|
||||||
|
SVGA3dSurfaceAllFlags svga3d_flags_64 =
|
||||||
|
SVGA3D_FLAGS_64(req->svga3d_flags_upper_32_bits,
|
||||||
|
req->base.svga3d_flags);
|
||||||
|
|
||||||
|
if (!dev_priv->has_sm4_1) {
|
||||||
|
/*
|
||||||
|
* If SM4_1 is not support then cannot send 64-bit flag to
|
||||||
|
* device.
|
||||||
|
*/
|
||||||
|
if (req->svga3d_flags_upper_32_bits != 0)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (req->base.multisample_count != 0)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (req->multisample_pattern != SVGA3D_MS_PATTERN_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (req->quality_level != SVGA3D_MS_QUALITY_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((svga3d_flags_64 & SVGA3D_SURFACE_MULTISAMPLE) &&
|
||||||
|
req->base.multisample_count == 0)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (req->base.mip_levels > DRM_VMW_MAX_MIP_LEVELS)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (unlikely(vmw_user_surface_size == 0))
|
||||||
|
vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
|
||||||
|
128;
|
||||||
|
|
||||||
|
size = vmw_user_surface_size + 128;
|
||||||
|
|
||||||
|
/* Define a surface based on the parameters. */
|
||||||
|
ret = vmw_surface_gb_priv_define(dev,
|
||||||
|
size,
|
||||||
|
svga3d_flags_64,
|
||||||
|
req->base.format,
|
||||||
|
req->base.drm_surface_flags &
|
||||||
|
drm_vmw_surface_flag_scanout,
|
||||||
|
req->base.mip_levels,
|
||||||
|
req->base.multisample_count,
|
||||||
|
req->base.array_size,
|
||||||
|
req->base.base_size,
|
||||||
|
req->multisample_pattern,
|
||||||
|
req->quality_level,
|
||||||
|
&srf);
|
||||||
|
if (unlikely(ret != 0))
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
user_srf = container_of(srf, struct vmw_user_surface, srf);
|
||||||
|
if (drm_is_primary_client(file_priv))
|
||||||
|
user_srf->master = drm_master_get(file_priv->master);
|
||||||
|
|
||||||
|
ret = ttm_read_lock(&dev_priv->reservation_sem, true);
|
||||||
|
if (unlikely(ret != 0))
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
res = &user_srf->srf.res;
|
||||||
|
|
||||||
|
if (req->base.buffer_handle != SVGA3D_INVALID_ID) {
|
||||||
|
ret = vmw_user_bo_lookup(tfile, req->base.buffer_handle,
|
||||||
|
&res->backup,
|
||||||
|
&user_srf->backup_base);
|
||||||
|
if (ret == 0) {
|
||||||
|
if (res->backup->base.num_pages * PAGE_SIZE <
|
||||||
|
res->backup_size) {
|
||||||
|
DRM_ERROR("Surface backup buffer too small.\n");
|
||||||
|
vmw_bo_unreference(&res->backup);
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto out_unlock;
|
||||||
|
} else {
|
||||||
|
backup_handle = req->base.buffer_handle;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else if (req->base.drm_surface_flags &
|
||||||
|
drm_vmw_surface_flag_create_buffer)
|
||||||
|
ret = vmw_user_bo_alloc(dev_priv, tfile,
|
||||||
|
res->backup_size,
|
||||||
|
req->base.drm_surface_flags &
|
||||||
|
drm_vmw_surface_flag_shareable,
|
||||||
|
&backup_handle,
|
||||||
|
&res->backup,
|
||||||
|
&user_srf->backup_base);
|
||||||
|
|
||||||
|
if (unlikely(ret != 0)) {
|
||||||
|
vmw_resource_unreference(&res);
|
||||||
|
goto out_unlock;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = vmw_resource_reference(res);
|
||||||
|
ret = ttm_prime_object_init(tfile, res->backup_size, &user_srf->prime,
|
||||||
|
req->base.drm_surface_flags &
|
||||||
|
drm_vmw_surface_flag_shareable,
|
||||||
|
VMW_RES_SURFACE,
|
||||||
|
&vmw_user_surface_base_release, NULL);
|
||||||
|
|
||||||
|
if (unlikely(ret != 0)) {
|
||||||
|
vmw_resource_unreference(&tmp);
|
||||||
|
vmw_resource_unreference(&res);
|
||||||
|
goto out_unlock;
|
||||||
|
}
|
||||||
|
|
||||||
|
rep->handle = user_srf->prime.base.hash.key;
|
||||||
|
rep->backup_size = res->backup_size;
|
||||||
|
if (res->backup) {
|
||||||
|
rep->buffer_map_handle =
|
||||||
|
drm_vma_node_offset_addr(&res->backup->base.vma_node);
|
||||||
|
rep->buffer_size = res->backup->base.num_pages * PAGE_SIZE;
|
||||||
|
rep->buffer_handle = backup_handle;
|
||||||
|
} else {
|
||||||
|
rep->buffer_map_handle = 0;
|
||||||
|
rep->buffer_size = 0;
|
||||||
|
rep->buffer_handle = SVGA3D_INVALID_ID;
|
||||||
|
}
|
||||||
|
|
||||||
|
vmw_resource_unreference(&res);
|
||||||
|
|
||||||
|
out_unlock:
|
||||||
|
ttm_read_unlock(&dev_priv->reservation_sem);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vmw_gb_surface_reference_internal - Ioctl function implementing
|
||||||
|
* the user surface reference functionality.
|
||||||
|
*
|
||||||
|
* @dev: Pointer to a struct drm_device.
|
||||||
|
* @req: Pointer to user-space request surface arg.
|
||||||
|
* @rep: Pointer to response to user-space.
|
||||||
|
* @file_priv: Pointer to a drm file private structure.
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
vmw_gb_surface_reference_internal(struct drm_device *dev,
|
||||||
|
struct drm_vmw_surface_arg *req,
|
||||||
|
struct drm_vmw_gb_surface_ref_ext_rep *rep,
|
||||||
|
struct drm_file *file_priv)
|
||||||
|
{
|
||||||
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
||||||
|
struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
|
||||||
|
struct vmw_surface *srf;
|
||||||
|
struct vmw_user_surface *user_srf;
|
||||||
|
struct ttm_base_object *base;
|
||||||
|
uint32_t backup_handle;
|
||||||
|
int ret = -EINVAL;
|
||||||
|
|
||||||
|
ret = vmw_surface_handle_reference(dev_priv, file_priv, req->sid,
|
||||||
|
req->handle_type, &base);
|
||||||
|
if (unlikely(ret != 0))
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
user_srf = container_of(base, struct vmw_user_surface, prime.base);
|
||||||
|
srf = &user_srf->srf;
|
||||||
|
if (!srf->res.backup) {
|
||||||
|
DRM_ERROR("Shared GB surface is missing a backup buffer.\n");
|
||||||
|
goto out_bad_resource;
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_lock(&dev_priv->cmdbuf_mutex); /* Protect res->backup */
|
||||||
|
ret = vmw_user_bo_reference(tfile, srf->res.backup, &backup_handle);
|
||||||
|
mutex_unlock(&dev_priv->cmdbuf_mutex);
|
||||||
|
|
||||||
|
if (unlikely(ret != 0)) {
|
||||||
|
DRM_ERROR("Could not add a reference to a GB surface "
|
||||||
|
"backup buffer.\n");
|
||||||
|
(void) ttm_ref_object_base_unref(tfile, base->hash.key,
|
||||||
|
TTM_REF_USAGE);
|
||||||
|
goto out_bad_resource;
|
||||||
|
}
|
||||||
|
|
||||||
|
rep->creq.base.svga3d_flags = SVGA3D_FLAGS_LOWER_32(srf->flags);
|
||||||
|
rep->creq.base.format = srf->format;
|
||||||
|
rep->creq.base.mip_levels = srf->mip_levels[0];
|
||||||
|
rep->creq.base.drm_surface_flags = 0;
|
||||||
|
rep->creq.base.multisample_count = srf->multisample_count;
|
||||||
|
rep->creq.base.autogen_filter = srf->autogen_filter;
|
||||||
|
rep->creq.base.array_size = srf->array_size;
|
||||||
|
rep->creq.base.buffer_handle = backup_handle;
|
||||||
|
rep->creq.base.base_size = srf->base_size;
|
||||||
|
rep->crep.handle = user_srf->prime.base.hash.key;
|
||||||
|
rep->crep.backup_size = srf->res.backup_size;
|
||||||
|
rep->crep.buffer_handle = backup_handle;
|
||||||
|
rep->crep.buffer_map_handle =
|
||||||
|
drm_vma_node_offset_addr(&srf->res.backup->base.vma_node);
|
||||||
|
rep->crep.buffer_size = srf->res.backup->base.num_pages * PAGE_SIZE;
|
||||||
|
|
||||||
|
rep->creq.version = drm_vmw_gb_surface_v1;
|
||||||
|
rep->creq.svga3d_flags_upper_32_bits =
|
||||||
|
SVGA3D_FLAGS_UPPER_32(srf->flags);
|
||||||
|
rep->creq.multisample_pattern = srf->multisample_pattern;
|
||||||
|
rep->creq.quality_level = srf->quality_level;
|
||||||
|
rep->creq.must_be_zero = 0;
|
||||||
|
|
||||||
|
out_bad_resource:
|
||||||
|
ttm_base_object_unref(&base);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
|
@ -69,6 +69,8 @@ extern "C" {
|
||||||
#define DRM_VMW_GB_SURFACE_REF 24
|
#define DRM_VMW_GB_SURFACE_REF 24
|
||||||
#define DRM_VMW_SYNCCPU 25
|
#define DRM_VMW_SYNCCPU 25
|
||||||
#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
|
#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
|
||||||
|
#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
|
||||||
|
#define DRM_VMW_GB_SURFACE_REF_EXT 28
|
||||||
|
|
||||||
/*************************************************************************/
|
/*************************************************************************/
|
||||||
/**
|
/**
|
||||||
|
@ -80,6 +82,9 @@ extern "C" {
|
||||||
*
|
*
|
||||||
* DRM_VMW_PARAM_OVERLAY_IOCTL:
|
* DRM_VMW_PARAM_OVERLAY_IOCTL:
|
||||||
* Does the driver support the overlay ioctl.
|
* Does the driver support the overlay ioctl.
|
||||||
|
*
|
||||||
|
* DRM_VMW_PARAM_SM4_1
|
||||||
|
* SM4_1 support is enabled.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define DRM_VMW_PARAM_NUM_STREAMS 0
|
#define DRM_VMW_PARAM_NUM_STREAMS 0
|
||||||
|
@ -95,6 +100,8 @@ extern "C" {
|
||||||
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
|
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
|
||||||
#define DRM_VMW_PARAM_SCREEN_TARGET 11
|
#define DRM_VMW_PARAM_SCREEN_TARGET 11
|
||||||
#define DRM_VMW_PARAM_DX 12
|
#define DRM_VMW_PARAM_DX 12
|
||||||
|
#define DRM_VMW_PARAM_HW_CAPS2 13
|
||||||
|
#define DRM_VMW_PARAM_SM4_1 14
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* enum drm_vmw_handle_type - handle type for ref ioctls
|
* enum drm_vmw_handle_type - handle type for ref ioctls
|
||||||
|
@ -1104,6 +1111,106 @@ struct drm_vmw_handle_close_arg {
|
||||||
};
|
};
|
||||||
#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
|
#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
|
||||||
|
|
||||||
|
/*************************************************************************/
|
||||||
|
/**
|
||||||
|
* DRM_VMW_GB_SURFACE_CREATE_EXT - Create a host guest-backed surface.
|
||||||
|
*
|
||||||
|
* Allocates a surface handle and queues a create surface command
|
||||||
|
* for the host on the first use of the surface. The surface ID can
|
||||||
|
* be used as the surface ID in commands referencing the surface.
|
||||||
|
*
|
||||||
|
* This new command extends DRM_VMW_GB_SURFACE_CREATE by adding version
|
||||||
|
* parameter and 64 bit svga flag.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* enum drm_vmw_surface_version
|
||||||
|
*
|
||||||
|
* @drm_vmw_surface_gb_v1: Corresponds to current gb surface format with
|
||||||
|
* svga3d surface flags split into 2, upper half and lower half.
|
||||||
|
*/
|
||||||
|
enum drm_vmw_surface_version {
|
||||||
|
drm_vmw_gb_surface_v1
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct drm_vmw_gb_surface_create_ext_req
|
||||||
|
*
|
||||||
|
* @base: Surface create parameters.
|
||||||
|
* @version: Version of surface create ioctl.
|
||||||
|
* @svga3d_flags_upper_32_bits: Upper 32 bits of svga3d flags.
|
||||||
|
* @multisample_pattern: Multisampling pattern when msaa is supported.
|
||||||
|
* @quality_level: Precision settings for each sample.
|
||||||
|
* @must_be_zero: Reserved for future usage.
|
||||||
|
*
|
||||||
|
* Input argument to the DRM_VMW_GB_SURFACE_CREATE_EXT Ioctl.
|
||||||
|
* Part of output argument for the DRM_VMW_GB_SURFACE_REF_EXT Ioctl.
|
||||||
|
*/
|
||||||
|
struct drm_vmw_gb_surface_create_ext_req {
|
||||||
|
struct drm_vmw_gb_surface_create_req base;
|
||||||
|
enum drm_vmw_surface_version version;
|
||||||
|
uint32_t svga3d_flags_upper_32_bits;
|
||||||
|
SVGA3dMSPattern multisample_pattern;
|
||||||
|
SVGA3dMSQualityLevel quality_level;
|
||||||
|
uint64_t must_be_zero;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* union drm_vmw_gb_surface_create_ext_arg
|
||||||
|
*
|
||||||
|
* @req: Input argument as described above.
|
||||||
|
* @rep: Output argument as described above.
|
||||||
|
*
|
||||||
|
* Argument to the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl.
|
||||||
|
*/
|
||||||
|
union drm_vmw_gb_surface_create_ext_arg {
|
||||||
|
struct drm_vmw_gb_surface_create_rep rep;
|
||||||
|
struct drm_vmw_gb_surface_create_ext_req req;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*************************************************************************/
|
||||||
|
/**
|
||||||
|
* DRM_VMW_GB_SURFACE_REF_EXT - Reference a host surface.
|
||||||
|
*
|
||||||
|
* Puts a reference on a host surface with a given handle, as previously
|
||||||
|
* returned by the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl.
|
||||||
|
* A reference will make sure the surface isn't destroyed while we hold
|
||||||
|
* it and will allow the calling client to use the surface handle in
|
||||||
|
* the command stream.
|
||||||
|
*
|
||||||
|
* On successful return, the Ioctl returns the surface information given
|
||||||
|
* to and returned from the DRM_VMW_GB_SURFACE_CREATE_EXT ioctl.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct drm_vmw_gb_surface_ref_ext_rep
|
||||||
|
*
|
||||||
|
* @creq: The data used as input when the surface was created, as described
|
||||||
|
* above at "struct drm_vmw_gb_surface_create_ext_req"
|
||||||
|
* @crep: Additional data output when the surface was created, as described
|
||||||
|
* above at "struct drm_vmw_gb_surface_create_rep"
|
||||||
|
*
|
||||||
|
* Output Argument to the DRM_VMW_GB_SURFACE_REF_EXT ioctl.
|
||||||
|
*/
|
||||||
|
struct drm_vmw_gb_surface_ref_ext_rep {
|
||||||
|
struct drm_vmw_gb_surface_create_ext_req creq;
|
||||||
|
struct drm_vmw_gb_surface_create_rep crep;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* union drm_vmw_gb_surface_reference_ext_arg
|
||||||
|
*
|
||||||
|
* @req: Input data as described above at "struct drm_vmw_surface_arg"
|
||||||
|
* @rep: Output data as described above at
|
||||||
|
* "struct drm_vmw_gb_surface_ref_ext_rep"
|
||||||
|
*
|
||||||
|
* Argument to the DRM_VMW_GB_SURFACE_REF Ioctl.
|
||||||
|
*/
|
||||||
|
union drm_vmw_gb_surface_reference_ext_arg {
|
||||||
|
struct drm_vmw_gb_surface_ref_ext_rep rep;
|
||||||
|
struct drm_vmw_surface_arg req;
|
||||||
|
};
|
||||||
|
|
||||||
#if defined(__cplusplus)
|
#if defined(__cplusplus)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue