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clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
Meson8m2 has a GP_PLL clock (similar to GP0_PLL on GXBB/GXL/GXM) which is used as input for the VPU clocks. The only supported frequency (based on Amlogic's vendor kernel sources) is 364MHz which is achieved using the following parameters: - input: XTAL (24MHz) - M = 182 - N = 3 - OD = 2 ^ 2 Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190324151104.18397-4-martin.blumenstingl@googlemail.com
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2 changed files with 66 additions and 1 deletions
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@ -1703,6 +1703,64 @@ static struct clk_regmap meson8b_mali = {
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},
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};
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static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
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PLL_PARAMS(182, 3),
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{ /* sentinel */ },
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};
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static struct clk_regmap meson8m2_gp_pll_dco = {
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.data = &(struct meson_clk_pll_data){
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.en = {
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.reg_off = HHI_GP_PLL_CNTL,
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.shift = 30,
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.width = 1,
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},
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.m = {
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.reg_off = HHI_GP_PLL_CNTL,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = HHI_GP_PLL_CNTL,
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.shift = 9,
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.width = 5,
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},
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.l = {
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.reg_off = HHI_GP_PLL_CNTL,
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.shift = 31,
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.width = 1,
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},
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.rst = {
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.reg_off = HHI_GP_PLL_CNTL,
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.shift = 29,
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.width = 1,
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},
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.table = meson8m2_gp_pll_params_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "gp_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap meson8m2_gp_pll = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_GP_PLL_CNTL,
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.shift = 16,
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.width = 2,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "gp_pll",
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "gp_pll_dco" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
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@ -2338,6 +2396,8 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
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[CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
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[CLKID_MALI_1] = &meson8b_mali_1.hw,
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[CLKID_MALI] = &meson8b_mali.hw,
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[CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
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[CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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@ -2500,6 +2560,8 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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&meson8b_mali_1_div,
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&meson8b_mali_1,
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&meson8b_mali,
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&meson8m2_gp_pll_dco,
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&meson8m2_gp_pll,
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};
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static const struct meson8b_clk_reset_line {
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@ -19,6 +19,7 @@
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
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#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
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#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
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#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
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@ -146,8 +147,10 @@
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#define CLKID_MALI_1_SEL 178
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#define CLKID_MALI_1_DIV 179
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#define CLKID_MALI_1 180
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#define CLKID_GP_PLL_DCO 181
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#define CLKID_GP_PLL 182
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#define CLK_NR_CLKS 181
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#define CLK_NR_CLKS 183
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/*
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* include the CLKID and RESETID that have
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