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drm/i915/lrc: Skip no-op per-bb buffer on gen9
Since we inherited the context image setup from gen8 which needed a per-bb workaround (for GPGPU), we are submitting an empty per-bb buffer on gen9. Now that we can skip adding the buffer to the context image, remove the dangling per-bb. This slightly improves execution latency, most notably on an idle engine. References: https://bugs.freedesktop.org/show_bug.cgi?id=87725 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170921135444.27330-2-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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1 changed files with 1 additions and 8 deletions
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@ -1184,13 +1184,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
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return batch;
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}
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static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
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{
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*batch++ = MI_BATCH_BUFFER_END;
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return batch;
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}
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#define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
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static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
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@ -1247,7 +1240,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
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return 0;
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case 9:
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wa_bb_fn[0] = gen9_init_indirectctx_bb;
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wa_bb_fn[1] = gen9_init_perctx_bb;
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wa_bb_fn[1] = NULL;
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break;
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case 8:
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wa_bb_fn[0] = gen8_init_indirectctx_bb;
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