mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-04 08:08:54 +00:00
ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASK
[ Upstream commit5aef1ff239
] The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on i.MX7ULP. Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for these platform, the FIFO watermark mask should be updated according to the fifo_depth. Fixes:a860fac420
("ASoC: fsl_sai: Add support for imx7ulp/imx8mq") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
115da6e650
commit
b8ae2bf5cc
2 changed files with 4 additions and 3 deletions
|
@ -680,10 +680,11 @@ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
|
|||
regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
|
||||
|
||||
regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
|
||||
FSL_SAI_CR1_RFW_MASK,
|
||||
FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
|
||||
sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
|
||||
regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
|
||||
FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
|
||||
FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
|
||||
FSL_SAI_MAXBURST_RX - 1);
|
||||
|
||||
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
|
||||
&sai->dma_params_rx);
|
||||
|
|
|
@ -94,7 +94,7 @@
|
|||
#define FSL_SAI_CSR_FRDE BIT(0)
|
||||
|
||||
/* SAI Transmit and Receive Configuration 1 Register */
|
||||
#define FSL_SAI_CR1_RFW_MASK 0x1f
|
||||
#define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
|
||||
|
||||
/* SAI Transmit and Receive Configuration 2 Register */
|
||||
#define FSL_SAI_CR2_SYNC BIT(30)
|
||||
|
|
Loading…
Reference in a new issue