drm/i915/tgl+: Sanitize DKL PHY register definitions
Not all Dekel PHY registers have a lane instance, so having to specify this when using them is awkward. It makes more sense to define each PHY register with its full internal PHY offset where bits 15:12 is the lane for lane-instanced PHY registers and just a register bank index for other PHY registers. This way lane-instanced registers can be referred to with the (tc_port, lane) parameters, while other registers just with a tc_port parameter. An additional benefit of this change is to prevent passing a Dekel register to a generic MMIO access function or vice versa. v2: - Fix parameter reuse in the DKL_REG_MMIO definition. v3: - Rebase on latest patchset version. Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221025114457.2191004-3-imre.deak@intel.com
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@ -1264,11 +1264,11 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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for (ln = 0; ln < 2; ln++) {
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int level;
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intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 0);
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intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
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level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
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DKL_TX_PRESHOOT_COEFF_MASK |
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DKL_TX_DE_EMPAHSIS_COEFF_MASK |
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DKL_TX_VSWING_CONTROL_MASK,
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@ -1278,7 +1278,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
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DKL_TX_PRESHOOT_COEFF_MASK |
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DKL_TX_DE_EMPAHSIS_COEFF_MASK |
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DKL_TX_VSWING_CONTROL_MASK,
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@ -1286,7 +1286,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
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DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
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DKL_TX_DP20BITMODE, 0);
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if (IS_ALDERLAKE_P(dev_priv)) {
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@ -1305,7 +1305,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
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val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
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}
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
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intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
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DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
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DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
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val);
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@ -2018,8 +2018,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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return;
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if (DISPLAY_VER(dev_priv) >= 12) {
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ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0);
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ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1);
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ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
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ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
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} else {
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ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
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ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
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@ -2080,8 +2080,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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}
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if (DISPLAY_VER(dev_priv) >= 12) {
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0);
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1);
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
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intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
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} else {
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intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
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intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
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@ -3086,7 +3086,7 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
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int ln;
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for (ln = 0; ln < 2; ln++)
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intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port), ln, DKL_PCS_DW5_CORE_SOFTRESET, 0);
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intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
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}
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static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
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@ -532,7 +532,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
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tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
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if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port), 2) &
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if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
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DKL_CMN_UC_DW27_UC_HEALTH, 1))
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drm_warn(&dev_priv->drm,
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"Timeout waiting TC uC health\n");
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@ -12,7 +12,7 @@
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#include "intel_dkl_phy_regs.h"
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static void
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dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx)
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dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
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{
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enum tc_port tc_port = DKL_REG_TC_PORT(reg);
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@ -20,28 +20,27 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx)
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intel_de_write(i915,
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HIP_INDEX_REG(tc_port),
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HIP_INDEX_VAL(tc_port, idx));
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HIP_INDEX_VAL(tc_port, reg.bank_idx));
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}
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/**
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* intel_dkl_phy_read - read a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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*
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* Read the @reg Dekel PHY register.
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*
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* Returns the read value.
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*/
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u32
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intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln)
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intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
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{
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u32 val;
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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val = intel_de_read(i915, reg);
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dkl_phy_set_hip_idx(i915, reg);
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val = intel_de_read(i915, DKL_REG_MMIO(reg));
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spin_unlock(&i915->display.dkl.phy_lock);
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@ -52,18 +51,17 @@ intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln)
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* intel_dkl_phy_write - write a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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* @val: value to write
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*
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* Write @val to the @reg Dekel PHY register.
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*/
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void
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intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val)
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intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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intel_de_write(i915, reg, val);
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dkl_phy_set_hip_idx(i915, reg);
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intel_de_write(i915, DKL_REG_MMIO(reg), val);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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@ -72,7 +70,6 @@ intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 v
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* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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* @clear: mask to clear
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* @set: mask to set
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*
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@ -80,12 +77,12 @@ intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 v
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* this value back to the register if the value differs from the read one.
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*/
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void
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intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set)
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intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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intel_de_rmw(i915, reg, clear, set);
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dkl_phy_set_hip_idx(i915, reg);
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intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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@ -94,17 +91,16 @@ intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 cle
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* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @ln: lane instance of @reg
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*
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* Read the @reg Dekel PHY register without returning the read value.
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*/
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void
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intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln)
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intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg, ln);
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intel_de_posting_read(i915, reg);
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dkl_phy_set_hip_idx(i915, reg);
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intel_de_posting_read(i915, DKL_REG_MMIO(reg));
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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@ -8,17 +8,17 @@
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#include <linux/types.h>
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#include "i915_reg_defs.h"
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#include "intel_dkl_phy_regs.h"
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struct drm_i915_private;
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u32
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intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln);
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intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
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void
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intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val);
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intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val);
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void
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intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set);
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intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
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void
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intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln);
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intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
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#endif /* __INTEL_DKL_PHY_H__ */
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@ -6,6 +6,13 @@
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#ifndef __INTEL_DKL_PHY_REGS__
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#define __INTEL_DKL_PHY_REGS__
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#include <linux/types.h>
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struct intel_dkl_phy_reg {
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u32 reg:24;
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u32 bank_idx:4;
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};
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#define _DKL_PHY1_BASE 0x168000
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#define _DKL_PHY2_BASE 0x169000
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#define _DKL_PHY3_BASE 0x16A000
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(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
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/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
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#define _DKL_PCS_DW5 0x14
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#define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, \
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#define DKL_REG_MMIO(__reg) _MMIO((__reg).reg)
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#define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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_DKL_PCS_DW5)
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_DKL_PHY2_BASE)
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#define _DKL_BANK_SHIFT 12
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#define _DKL_REG_BANK_OFFSET(phy_offset) \
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((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1))
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#define _DKL_REG_BANK_IDX(phy_offset) \
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(((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)
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#define _DKL_REG(tc_port, phy_offset) \
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((const struct intel_dkl_phy_reg) { \
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.reg = _DKL_REG_PHY_BASE(tc_port) + \
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_DKL_REG_BANK_OFFSET(phy_offset), \
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.bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
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})
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#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
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_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
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#define _DKL_PCS_DW5_LN0 0x0014
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#define _DKL_PCS_DW5_LN1 0x1014
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#define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
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_DKL_PCS_DW5_LN0, \
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_DKL_PCS_DW5_LN1)
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#define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11)
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#define _DKL_PLL_DIV0 0x200
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#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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#define _DKL_PLL_DIV0 0x2200
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#define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \
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_DKL_PLL_DIV0)
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#define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
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#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
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DKL_PLL_DIV0_FBPREDIV_MASK | \
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DKL_PLL_DIV0_FBDIV_INT_MASK)
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#define _DKL_PLL_DIV1 0x204
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#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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#define _DKL_PLL_DIV1 0x2204
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#define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \
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_DKL_PLL_DIV1)
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#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
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#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
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#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
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#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
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#define _DKL_PLL_SSC 0x210
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#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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#define _DKL_PLL_SSC 0x2210
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#define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \
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_DKL_PLL_SSC)
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#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
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#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
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#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
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#define DKL_PLL_SSC_EN (1 << 9)
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#define _DKL_PLL_BIAS 0x214
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#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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#define _DKL_PLL_BIAS 0x2214
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#define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \
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_DKL_PLL_BIAS)
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#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
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#define DKL_PLL_BIAS_FBDIV_SHIFT (8)
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#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
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#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
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#define _DKL_PLL_TDC_COLDST_BIAS 0x218
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#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
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_DKL_PHY1_BASE, \
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_DKL_PHY2_BASE) + \
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#define _DKL_PLL_TDC_COLDST_BIAS 0x2218
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#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \
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_DKL_PLL_TDC_COLDST_BIAS)
|
||||
#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
|
||||
#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
|
||||
#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
|
||||
#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
|
||||
|
||||
#define _DKL_REFCLKIN_CTL 0x12C
|
||||
#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
#define _DKL_REFCLKIN_CTL 0x212C
|
||||
#define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \
|
||||
_DKL_REFCLKIN_CTL)
|
||||
/* Bits are the same as MG_REFCLKIN_CTL */
|
||||
|
||||
#define _DKL_CLKTOP2_HSCLKCTL 0xD4
|
||||
#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
#define _DKL_CLKTOP2_HSCLKCTL 0x20D4
|
||||
#define DKL_CLKTOP2_HSCLKCTL(rc_port) _DKL_REG(tc_port, \
|
||||
_DKL_CLKTOP2_HSCLKCTL)
|
||||
/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
|
||||
|
||||
#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
|
||||
#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
#define _DKL_CLKTOP2_CORECLKCTL1 0x20D8
|
||||
#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \
|
||||
_DKL_CLKTOP2_CORECLKCTL1)
|
||||
/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
|
||||
|
||||
#define _DKL_TX_DPCNTL0 0x2C0
|
||||
#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DPCNTL0)
|
||||
#define _DKL_TX_DPCNTL0_LN0 0x02C0
|
||||
#define _DKL_TX_DPCNTL0_LN1 0x12C0
|
||||
#define DKL_TX_DPCNTL0(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_DPCNTL0_LN0, \
|
||||
_DKL_TX_DPCNTL0_LN1)
|
||||
#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
|
||||
#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
|
||||
#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
|
||||
|
@ -121,59 +134,57 @@
|
|||
#define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
|
||||
#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
|
||||
|
||||
#define _DKL_TX_DPCNTL1 0x2C4
|
||||
#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DPCNTL1)
|
||||
#define _DKL_TX_DPCNTL1_LN0 0x02C4
|
||||
#define _DKL_TX_DPCNTL1_LN1 0x12C4
|
||||
#define DKL_TX_DPCNTL1(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_DPCNTL1_LN0, \
|
||||
_DKL_TX_DPCNTL1_LN1)
|
||||
/* Bits are the same as DKL_TX_DPCNTRL0 */
|
||||
|
||||
#define _DKL_TX_DPCNTL2 0x2C8
|
||||
#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DPCNTL2)
|
||||
#define _DKL_TX_DPCNTL2_LN0 0x02C8
|
||||
#define _DKL_TX_DPCNTL2_LN1 0x12C8
|
||||
#define DKL_TX_DPCNTL2(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_DPCNTL2_LN0, \
|
||||
_DKL_TX_DPCNTL2_LN1)
|
||||
#define DKL_TX_DP20BITMODE REG_BIT(2)
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3)
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5)
|
||||
#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
|
||||
|
||||
#define _DKL_TX_FW_CALIB 0x2F8
|
||||
#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_FW_CALIB)
|
||||
#define _DKL_TX_FW_CALIB_LN0 0x02F8
|
||||
#define _DKL_TX_FW_CALIB_LN1 0x12F8
|
||||
#define DKL_TX_FW_CALIB(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_FW_CALIB_LN0, \
|
||||
_DKL_TX_FW_CALIB_LN1)
|
||||
#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
|
||||
|
||||
#define _DKL_TX_PMD_LANE_SUS 0xD00
|
||||
#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_PMD_LANE_SUS)
|
||||
#define _DKL_TX_PMD_LANE_SUS_LN0 0x0D00
|
||||
#define _DKL_TX_PMD_LANE_SUS_LN1 0x1D00
|
||||
#define DKL_TX_PMD_LANE_SUS(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_PMD_LANE_SUS_LN0, \
|
||||
_DKL_TX_PMD_LANE_SUS_LN1)
|
||||
|
||||
#define _DKL_TX_DW17 0xDC4
|
||||
#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DW17)
|
||||
#define _DKL_TX_DW17_LN0 0x0DC4
|
||||
#define _DKL_TX_DW17_LN1 0x1DC4
|
||||
#define DKL_TX_DW17(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_DW17_LN0, \
|
||||
_DKL_TX_DW17_LN1)
|
||||
|
||||
#define _DKL_TX_DW18 0xDC8
|
||||
#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_TX_DW18)
|
||||
#define _DKL_TX_DW18_LN0 0x0DC8
|
||||
#define _DKL_TX_DW18_LN1 0x1DC8
|
||||
#define DKL_TX_DW18(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_TX_DW18_LN0, \
|
||||
_DKL_TX_DW18_LN1)
|
||||
|
||||
#define _DKL_DP_MODE 0xA0
|
||||
#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
_DKL_DP_MODE)
|
||||
#define _DKL_DP_MODE_LN0 0x00A0
|
||||
#define _DKL_DP_MODE_LN1 0x10A0
|
||||
#define DKL_DP_MODE(tc_port, ln) _DKL_REG_LN(tc_port, ln, \
|
||||
_DKL_DP_MODE_LN0, \
|
||||
_DKL_DP_MODE_LN1)
|
||||
|
||||
#define _DKL_CMN_UC_DW27 0x36C
|
||||
#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
|
||||
_DKL_PHY1_BASE, \
|
||||
_DKL_PHY2_BASE) + \
|
||||
#define _DKL_CMN_UC_DW27 0x236C
|
||||
#define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \
|
||||
_DKL_CMN_UC_DW27)
|
||||
#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
|
||||
|
||||
|
|
|
@ -3489,11 +3489,11 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
|||
* they are on different building blocks
|
||||
*/
|
||||
hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv,
|
||||
DKL_REFCLKIN_CTL(tc_port), 2);
|
||||
DKL_REFCLKIN_CTL(tc_port));
|
||||
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
|
||||
|
||||
hw_state->mg_clktop2_hsclkctl =
|
||||
intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2);
|
||||
intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port));
|
||||
hw_state->mg_clktop2_hsclkctl &=
|
||||
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
|
||||
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
|
||||
|
@ -3501,32 +3501,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
|
|||
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
|
||||
|
||||
hw_state->mg_clktop2_coreclkctl1 =
|
||||
intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2);
|
||||
intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port));
|
||||
hw_state->mg_clktop2_coreclkctl1 &=
|
||||
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
|
||||
|
||||
hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port), 2);
|
||||
hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port));
|
||||
val = DKL_PLL_DIV0_MASK;
|
||||
if (dev_priv->display.vbt.override_afc_startup)
|
||||
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
|
||||
hw_state->mg_pll_div0 &= val;
|
||||
|
||||
hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2);
|
||||
hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port));
|
||||
hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
|
||||
DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
|
||||
|
||||
hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2);
|
||||
hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port));
|
||||
hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
|
||||
DKL_PLL_SSC_STEP_LEN_MASK |
|
||||
DKL_PLL_SSC_STEP_NUM_MASK |
|
||||
DKL_PLL_SSC_EN);
|
||||
|
||||
hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2);
|
||||
hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port));
|
||||
hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
|
||||
DKL_PLL_BIAS_FBDIV_FRAC_MASK);
|
||||
|
||||
hw_state->mg_pll_tdc_coldst_bias =
|
||||
intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2);
|
||||
intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
|
||||
hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
|
||||
DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
|
||||
|
||||
|
@ -3715,57 +3715,57 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv,
|
|||
* though on different building block
|
||||
*/
|
||||
/* All the registers are RMW */
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port));
|
||||
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
|
||||
val |= hw_state->mg_refclkin_ctl;
|
||||
intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val);
|
||||
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port));
|
||||
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
|
||||
val |= hw_state->mg_clktop2_coreclkctl1;
|
||||
intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
|
||||
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port));
|
||||
val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
|
||||
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
|
||||
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
|
||||
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
|
||||
val |= hw_state->mg_clktop2_hsclkctl;
|
||||
intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
|
||||
|
||||
val = DKL_PLL_DIV0_MASK;
|
||||
if (dev_priv->display.vbt.override_afc_startup)
|
||||
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
|
||||
intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), 2, val,
|
||||
intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val,
|
||||
hw_state->mg_pll_div0);
|
||||
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port));
|
||||
val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
|
||||
DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
|
||||
val |= hw_state->mg_pll_div1;
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), val);
|
||||
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port));
|
||||
val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
|
||||
DKL_PLL_SSC_STEP_LEN_MASK |
|
||||
DKL_PLL_SSC_STEP_NUM_MASK |
|
||||
DKL_PLL_SSC_EN);
|
||||
val |= hw_state->mg_pll_ssc;
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), val);
|
||||
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port));
|
||||
val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
|
||||
DKL_PLL_BIAS_FBDIV_FRAC_MASK);
|
||||
val |= hw_state->mg_pll_bias;
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), val);
|
||||
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2);
|
||||
val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
|
||||
val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
|
||||
DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
|
||||
val |= hw_state->mg_pll_tdc_coldst_bias;
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2, val);
|
||||
intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
|
||||
|
||||
intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), 2);
|
||||
intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
|
||||
}
|
||||
|
||||
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
|
||||
|
|
Loading…
Reference in New Issue