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iommu/tegra-smmu: Split smmu_flush_ptc()

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smmu_flush_ptc() is used in two modes: one is to flush an individual
entry, the other is to flush all entries.  We know at the call site
which we require.  Split the function into smmu_flush_ptc_all() and
smmu_flush_ptc().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Russell King 2015-07-27 13:29:41 +01:00 committed by Thierry Reding
parent 4b3c7d1076
commit b8fe03827b
1 changed files with 13 additions and 13 deletions
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26
drivers/iommu/tegra-smmu.c
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@ -165,29 +165,29 @@ static void smmu_flush_dcache(struct page *page, unsigned long offset,
#endif
}
static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
{
smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
}
static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page,
unsigned long offset)
{
phys_addr_t phys = page ? page_to_phys(page) : 0;
phys_addr_t phys = page_to_phys(page);
u32 value;
if (page) {
offset &= ~(smmu->mc->soc->atom_size - 1);
offset &= ~(smmu->mc->soc->atom_size - 1);
if (smmu->mc->soc->num_address_bits > 32) {
if (smmu->mc->soc->num_address_bits > 32) {
#ifdef CONFIG_PHYS_ADDR_T_64BIT
value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK;
value = (phys >> 32) & SMMU_PTC_FLUSH_HI_MASK;
#else
value = 0;
value = 0;
#endif
smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
}
value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
} else {
value = SMMU_PTC_FLUSH_TYPE_ALL;
smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
}
value = (phys + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
smmu_writel(smmu, value, SMMU_PTC_FLUSH);
}
@ -894,7 +894,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
smmu_writel(smmu, value, SMMU_TLB_CONFIG);
smmu_flush_ptc(smmu, NULL, 0);
smmu_flush_ptc_all(smmu);
smmu_flush_tlb(smmu);
smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
smmu_flush(smmu);