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net: document SMII and correct phylink's new validation mechanism

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SMII has not been documented in the kernel, but information on this PHY
interface mode has been recently found. Document it, and correct the
recently introduced phylink handling for this interface mode.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/E1mmfVl-0075nP-14@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle) 2021-11-15 17:11:17 +00:00 committed by Jakub Kicinski
parent be0f6c4100
commit b9241f5413
3 changed files with 7 additions and 2 deletions
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5
Documentation/networking/phy.rst
View file

@ -237,6 +237,11 @@ negotiation results.
Some of the interface modes are described below:
``PHY_INTERFACE_MODE_SMII``
This is serial MII, clocked at 125MHz, supporting 100M and 10M speeds.
Some details can be found in
https://opencores.org/ocsvn/smii/smii/trunk/doc/SMII.pdf
``PHY_INTERFACE_MODE_1000BASEX``
This defines the 1000BASE-X single-lane serdes link as defined by the
802.3 standard section 36. The link operates at a fixed bit rate of

2
drivers/net/phy/phylink.c
View file

@ -336,6 +336,7 @@ void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface,
case PHY_INTERFACE_MODE_REVRMII:
case PHY_INTERFACE_MODE_RMII:
case PHY_INTERFACE_MODE_SMII:
case PHY_INTERFACE_MODE_REVMII:
case PHY_INTERFACE_MODE_MII:
caps |= MAC_10HD | MAC_10FD;
@ -385,7 +386,6 @@ void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface,
case PHY_INTERFACE_MODE_NA:
case PHY_INTERFACE_MODE_MAX:
case PHY_INTERFACE_MODE_SMII:
break;
}

2
include/linux/phy.h
View file

@ -99,7 +99,7 @@ extern const int phy_10gbit_features_array[1];
* @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay
* @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal RX delay
* @PHY_INTERFACE_MODE_RTBI: Reduced TBI
* @PHY_INTERFACE_MODE_SMII: ??? MII
* @PHY_INTERFACE_MODE_SMII: Serial MII
* @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface
* @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface
* @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax