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drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
3eb6e4795d
commit
b92c628712
7 changed files with 66 additions and 24 deletions
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@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
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#define amdgpu_dpm_force_performance_level(adev, l) \
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((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
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#define amdgpu_dpm_powergate_uvd(adev, g) \
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((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
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#define amdgpu_dpm_powergate_vce(adev, g) \
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((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
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#define amdgpu_dpm_get_current_power_state(adev) \
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((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
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@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
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((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
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(adev)->powerplay.pp_handle, msg_id))
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#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
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((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
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(adev)->powerplay.pp_handle, block_type, gate))
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#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
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((adev)->powerplay.pp_funcs->get_power_profile_mode(\
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(adev)->powerplay.pp_handle, buf))
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@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
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((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
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(adev)->powerplay.pp_handle, type, parameter, size))
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#define amdgpu_dpm_powergate_mmhub(adev) \
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((adev)->powerplay.pp_funcs->powergate_mmhub( \
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(adev)->powerplay.pp_handle))
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struct amdgpu_dpm {
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struct amdgpu_ps *ps;
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/* number of valid power states */
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@ -1729,10 +1729,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
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void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
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{
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if (adev->powerplay.pp_funcs->powergate_uvd) {
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if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
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/* enable/disable UVD */
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mutex_lock(&adev->pm.mutex);
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amdgpu_dpm_powergate_uvd(adev, !enable);
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amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
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mutex_unlock(&adev->pm.mutex);
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} else {
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if (enable) {
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@ -1751,10 +1751,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
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void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
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{
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if (adev->powerplay.pp_funcs->powergate_vce) {
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if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
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/* enable/disable VCE */
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mutex_lock(&adev->pm.mutex);
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amdgpu_dpm_powergate_vce(adev, !enable);
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amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
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mutex_unlock(&adev->pm.mutex);
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} else {
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if (enable) {
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@ -6767,6 +6767,19 @@ static int ci_dpm_read_sensor(void *handle, int idx,
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}
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}
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static int ci_set_powergating_by_smu(void *handle,
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uint32_t block_type, bool gate)
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{
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switch (block_type) {
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case AMD_IP_BLOCK_TYPE_UVD:
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ci_dpm_powergate_uvd(handle, gate);
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break;
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default:
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break;
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}
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return 0;
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}
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static const struct amd_ip_funcs ci_dpm_ip_funcs = {
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.name = "ci_dpm",
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.early_init = ci_dpm_early_init,
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@ -6804,7 +6817,7 @@ static const struct amd_pm_funcs ci_dpm_funcs = {
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.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
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.force_performance_level = &ci_dpm_force_performance_level,
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.vblank_too_short = &ci_dpm_vblank_too_short,
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.powergate_uvd = &ci_dpm_powergate_uvd,
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.set_powergating_by_smu = &ci_set_powergating_by_smu,
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.set_fan_control_mode = &ci_dpm_set_fan_control_mode,
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.get_fan_control_mode = &ci_dpm_get_fan_control_mode,
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.set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
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@ -3306,6 +3306,19 @@ static int kv_dpm_read_sensor(void *handle, int idx,
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}
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}
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static int kv_set_powergating_by_smu(void *handle,
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uint32_t block_type, bool gate)
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{
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switch (block_type) {
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case AMD_IP_BLOCK_TYPE_UVD:
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kv_dpm_powergate_uvd(handle, gate);
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break;
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default:
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break;
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}
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return 0;
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}
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static const struct amd_ip_funcs kv_dpm_ip_funcs = {
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.name = "kv_dpm",
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.early_init = kv_dpm_early_init,
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@ -3342,7 +3355,7 @@ static const struct amd_pm_funcs kv_dpm_funcs = {
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.print_power_state = &kv_dpm_print_power_state,
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.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
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.force_performance_level = &kv_dpm_force_performance_level,
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.powergate_uvd = &kv_dpm_powergate_uvd,
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.set_powergating_by_smu = kv_set_powergating_by_smu,
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.enable_bapm = &kv_dpm_enable_bapm,
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.get_vce_clock_state = amdgpu_get_vce_clock_state,
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.check_state_equal = kv_check_state_equal,
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@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
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RENG_EXECUTE_ON_REG_UPDATE, 1);
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WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
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if (adev->powerplay.pp_funcs->powergate_mmhub)
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amdgpu_dpm_powergate_mmhub(adev);
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if (adev->powerplay.pp_funcs->set_powergating_by_smu)
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amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
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} else {
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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@ -232,13 +232,13 @@ struct amd_pm_funcs {
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void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
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int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
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/* export to amdgpu */
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void (*powergate_uvd)(void *handle, bool gate);
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void (*powergate_vce)(void *handle, bool gate);
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struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
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int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
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enum amd_pm_state_type *user_state);
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int (*load_firmware)(void *handle);
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int (*wait_for_fw_loading_complete)(void *handle);
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int (*set_powergating_by_smu)(void *handle,
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uint32_t block_type, bool gate);
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int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
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int (*set_power_limit)(void *handle, uint32_t n);
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int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
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@ -269,7 +269,6 @@ struct amd_pm_funcs {
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int (*get_power_profile_mode)(void *handle, char *buf);
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int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
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int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
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int (*powergate_mmhub)(void *handle);
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};
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#endif
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@ -244,6 +244,7 @@ static int pp_set_powergating_state(void *handle,
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/* Enable/disable GFX per cu powergating through SMU */
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return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
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state == AMD_PG_STATE_GATE);
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}
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static int pp_suspend(void *handle)
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@ -1183,14 +1184,36 @@ static int pp_dpm_powergate_mmhub(void *handle)
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return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
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}
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static int pp_set_powergating_by_smu(void *handle,
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uint32_t block_type, bool gate)
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{
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int ret = 0;
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switch (block_type) {
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case AMD_IP_BLOCK_TYPE_UVD:
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case AMD_IP_BLOCK_TYPE_VCN:
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pp_dpm_powergate_uvd(handle, gate);
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break;
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case AMD_IP_BLOCK_TYPE_VCE:
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pp_dpm_powergate_vce(handle, gate);
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break;
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case AMD_IP_BLOCK_TYPE_GMC:
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pp_dpm_powergate_mmhub(handle);
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break;
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case AMD_IP_BLOCK_TYPE_GFX:
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break;
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default:
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break;
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}
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return ret;
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}
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static const struct amd_pm_funcs pp_dpm_funcs = {
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.load_firmware = pp_dpm_load_fw,
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.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
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.force_performance_level = pp_dpm_force_performance_level,
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.get_performance_level = pp_dpm_get_performance_level,
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.get_current_power_state = pp_dpm_get_current_power_state,
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.powergate_vce = pp_dpm_powergate_vce,
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.powergate_uvd = pp_dpm_powergate_uvd,
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.dispatch_tasks = pp_dpm_dispatch_tasks,
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.set_fan_control_mode = pp_dpm_set_fan_control_mode,
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.get_fan_control_mode = pp_dpm_get_fan_control_mode,
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@ -1210,6 +1233,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
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.get_vce_clock_state = pp_dpm_get_vce_clock_state,
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.switch_power_profile = pp_dpm_switch_power_profile,
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.set_clockgating_by_smu = pp_set_clockgating_by_smu,
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.set_powergating_by_smu = pp_set_powergating_by_smu,
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.get_power_profile_mode = pp_get_power_profile_mode,
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.set_power_profile_mode = pp_set_power_profile_mode,
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.odn_edit_dpm_table = pp_odn_edit_dpm_table,
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@ -1227,5 +1251,4 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
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.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
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.display_clock_voltage_request = pp_display_clock_voltage_request,
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.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
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.powergate_mmhub = pp_dpm_powergate_mmhub,
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};
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