dt-bindings: display: imx: hdmi: Convert binding to YAML
Convert the i.MX6 HDMI TX text binding to YAML. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
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Laurent Pinchart
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391ce40de5
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX6 DWC HDMI TX Encoder
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maintainers:
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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allOf:
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- $ref: ../bridge/synopsys,dw-hdmi.yaml#
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properties:
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compatible:
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enum:
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- fsl,imx6dl-hdmi
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- fsl,imx6q-hdmi
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reg-io-width:
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const: 1
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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ddc-i2c-bus:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The HDMI DDC bus can be connected to either a system I2C master or the
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functionally-reduced I2C master contained in the DWC HDMI. When connected
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to a system I2C master this property contains a phandle to that I2C
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master controller.
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gpr:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to the iomuxc-gpr region containing the HDMI multiplexer control
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register.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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This device has four video ports, corresponding to the four inputs of the
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HDMI multiplexer. Each port shall have a single endpoint.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: First input of the HDMI multiplexer
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Second input of the HDMI multiplexer
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: Third input of the HDMI multiplexer
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port@3:
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$ref: /schemas/graph.yaml#/properties/port
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description: Fourth input of the HDMI multiplexer
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anyOf:
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- required:
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- port@0
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- required:
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- port@1
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- required:
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- port@2
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- required:
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- port@3
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- gpr
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- interrupts
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6qdl-clock.h>
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hdmi: hdmi@120000 {
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reg = <0x00120000 0x9000>;
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interrupts = <0 115 0x04>;
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gpr = <&gpr>;
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clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
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<&clks IMX6QDL_CLK_HDMI_ISFR>;
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clock-names = "iahb", "isfr";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_hdmi>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_hdmi>;
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};
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};
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};
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};
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...
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@ -1,65 +0,0 @@
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Freescale i.MX6 DWC HDMI TX Encoder
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===================================
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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following device-specific properties.
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Required properties:
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- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
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- reg: See dw_hdmi.txt.
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- interrupts: HDMI interrupt number
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- clocks: See dw_hdmi.txt.
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- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
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- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
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numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
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Each port shall have a single endpoint.
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- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
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multiplexer control register.
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Optional properties
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- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
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or the functionally-reduced I2C master contained in the DWC HDMI. When
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connected to a system I2C master this property contains a phandle to that
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I2C master controller.
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Example:
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gpr: iomuxc-gpr@20e0000 {
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/* ... */
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};
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hdmi: hdmi@120000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-hdmi";
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reg = <0x00120000 0x9000>;
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interrupts = <0 115 0x04>;
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gpr = <&gpr>;
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clocks = <&clks 123>, <&clks 124>;
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clock-names = "iahb", "isfr";
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ddc-i2c-bus = <&i2c2>;
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port@0 {
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reg = <0>;
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hdmi_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_hdmi>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_hdmi>;
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};
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};
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};
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