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Blackfin serial driver: use new GPIO API
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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8c61362377
commit
b99ab54d4f
1 changed files with 19 additions and 20 deletions
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@ -1,5 +1,6 @@
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#include <linux/serial.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#define NR_PORTS 4
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@ -143,50 +144,48 @@ struct bfin_serial_res bfin_serial_resource[] = {
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int nr_ports = ARRAY_SIZE(bfin_serial_resource);
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#define DRIVER_NAME "bfin-uart"
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static void bfin_serial_hw_init(struct bfin_serial_port *uart)
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{
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#ifdef CONFIG_SERIAL_BFIN_UART0
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/* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
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bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
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bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
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peripheral_request(P_UART0_TX, DRIVER_NAME);
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peripheral_request(P_UART0_RX, DRIVER_NAME);
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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/* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
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bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
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bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
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peripheral_request(P_UART1_TX, DRIVER_NAME);
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peripheral_request(P_UART1_RX, DRIVER_NAME);
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#ifdef CONFIG_BFIN_UART1_CTSRTS
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/* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
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bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
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bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
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peripheral_request(P_UART1_RTS, DRIVER_NAME);
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peripheral_request(P_UART1_CTS DRIVER_NAME);
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#endif
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART2
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/* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
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bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
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bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
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peripheral_request(P_UART2_TX, DRIVER_NAME);
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peripheral_request(P_UART2_RX, DRIVER_NAME);
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART3
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/* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
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bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
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bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
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peripheral_request(P_UART3_TX, DRIVER_NAME);
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peripheral_request(P_UART3_RX, DRIVER_NAME);
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#ifdef CONFIG_BFIN_UART3_CTSRTS
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/* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
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bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
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bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
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peripheral_request(P_UART3_RTS, DRIVER_NAME);
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peripheral_request(P_UART3_CTS DRIVER_NAME);
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#endif
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#endif
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SSYNC();
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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if (uart->cts_pin >= 0) {
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gpio_request(uart->cts_pin, NULL);
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gpio_request(uart->cts_pin, DRIVER_NAME);
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gpio_direction_input(uart->cts_pin);
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}
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if (uart->rts_pin >= 0) {
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gpio_request(uart->rts_pin, NULL);
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gpio_request(uart->rts_pin, DRIVER_NAME);
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gpio_direction_output(uart->rts_pin);
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}
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#endif
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