PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
All RC complex drivers must call dw_pcie_setup_rc(). The ordering of the call shouldn't be too important other than being after any RC resets. There's a few calls of dw_pcie_setup_rc() left as drivers implementing suspend/resume need it. Link: https://lore.kernel.org/r/20201105211159.1814485-13-robh@kernel.org Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Minghuan Lian <minghuan.Lian@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Roy Zang <roy.zang@nxp.com> Cc: Yue Wang <yue.wang@Amlogic.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-omap@vger.kernel.org Cc: linux-samsung-soc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@axis.com Cc: linux-arm-msm@vger.kernel.org
This commit is contained in:
Rob Herring
Lorenzo Pieralisi
parent
59fbab1ae4
commit
b9ac0f9dc8
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@ -181,7 +181,6 @@ static int dra7xx_pcie_host_init(struct pcie_port *pp)
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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dw_pcie_setup_rc(pp);
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dra7xx_pcie_enable_interrupts(dra7xx);
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return 0;
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@ -372,7 +372,6 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
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phy_init(ep->phy);
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exynos_pcie_deassert_core_reset(ep);
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dw_pcie_setup_rc(pp);
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exynos_pcie_assert_reset(ep);
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exynos_pcie_enable_interrupts(ep);
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@ -834,7 +834,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp)
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imx6_pcie_init_phy(imx6_pcie);
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imx6_pcie_deassert_core_reset(imx6_pcie);
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imx6_setup_phy_mpll(imx6_pcie);
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dw_pcie_setup_rc(pp);
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return 0;
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}
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@ -807,8 +807,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
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if (ret)
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return ret;
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dw_pcie_setup_rc(pp);
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ks_pcie_stop_link(pci);
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ks_pcie_setup_rc_app_regs(ks_pcie);
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writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
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@ -136,8 +136,6 @@ static int ls_pcie_host_init(struct pcie_port *pp)
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ls_pcie_drop_msg_tlp(pcie);
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dw_pcie_setup_rc(pp);
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return 0;
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}
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@ -380,8 +380,6 @@ static int meson_pcie_host_init(struct pcie_port *pp)
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meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
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meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
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dw_pcie_setup_rc(pp);
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return 0;
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}
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@ -171,8 +171,6 @@ static int armada8k_pcie_host_init(struct pcie_port *pp)
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u32 reg;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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dw_pcie_setup_rc(pp);
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if (!dw_pcie_link_up(pci)) {
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/* Disable LTSSM state machine to enable configuration */
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reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
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@ -328,7 +328,6 @@ static int artpec6_pcie_host_init(struct pcie_port *pp)
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artpec6_pcie_init_phy(artpec6_pcie);
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artpec6_pcie_deassert_core_reset(artpec6_pcie);
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artpec6_pcie_wait_for_phy(artpec6_pcie);
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dw_pcie_setup_rc(pp);
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return 0;
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}
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@ -422,6 +422,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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goto err_free_msi;
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}
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dw_pcie_setup_rc(pp);
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dw_pcie_msi_init(pp);
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if (!dw_pcie_link_up(pci) && pci->ops->start_link) {
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@ -33,15 +33,7 @@ struct dw_plat_pcie_of_data {
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static const struct of_device_id dw_plat_pcie_of_match[];
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static int dw_plat_pcie_host_init(struct pcie_port *pp)
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{
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dw_pcie_setup_rc(pp);
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return 0;
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}
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static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
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.host_init = dw_plat_pcie_host_init,
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};
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static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
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@ -196,9 +196,6 @@ static int histb_pcie_host_init(struct pcie_port *pp)
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regval |= PCIE_WM_RC;
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histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
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/* setup root complex */
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dw_pcie_setup_rc(pp);
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return 0;
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}
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@ -405,8 +405,6 @@ static int kirin_pcie_host_init(struct pcie_port *pp)
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{
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pp->bridge->ops = &kirin_pci_ops;
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dw_pcie_setup_rc(pp);
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return 0;
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}
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@ -1280,7 +1280,6 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
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goto err_disable_phy;
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}
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dw_pcie_setup_rc(pp);
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qcom_ep_reset_deassert(pcie);
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return 0;
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@ -130,8 +130,6 @@ static int spear13xx_pcie_host_init(struct pcie_port *pp)
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spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
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dw_pcie_setup_rc(pp);
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/*
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* this controller support only 128 bytes read size, however its
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* default value in capability register is 512 bytes. So force
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@ -314,8 +314,6 @@ static int uniphier_pcie_host_init(struct pcie_port *pp)
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uniphier_pcie_irq_enable(priv);
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dw_pcie_setup_rc(pp);
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return 0;
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}
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