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arm64: errata: Expand speculative SSBS workaround
[ Upstream commit75b3c43eab] A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We worked around this for Cortex-X4 and Neoverse-V3, in commit:7187bb7d0b("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") ... as per their Software Developer Errata Notice (SDEN) documents: * Cortex-X4 SDEN v8.0, erratum 3194386: https://developer.arm.com/documentation/SDEN-2432808/0800/ * Neoverse-V3 SDEN v6.0, erratum 3312417: https://developer.arm.com/documentation/SDEN-2891958/0600/ Since then, similar errata have been published for a number of other Arm Ltd CPUs, for which the mitigation is the same. This is described in their respective SDEN documents: * Cortex-A710 SDEN v19.0, errataum 3324338 https://developer.arm.com/documentation/SDEN-1775101/1900/?lang=en * Cortex-A720 SDEN v11.0, erratum 3456091 https://developer.arm.com/documentation/SDEN-2439421/1100/?lang=en * Cortex-X2 SDEN v19.0, erratum 3324338 https://developer.arm.com/documentation/SDEN-1775100/1900/?lang=en * Cortex-X3 SDEN v14.0, erratum 3324335 https://developer.arm.com/documentation/SDEN-2055130/1400/?lang=en * Cortex-X925 SDEN v8.0, erratum 3324334 https://developer.arm.com/documentation/109108/800/?lang=en * Neoverse-N2 SDEN v17.0, erratum 3324339 https://developer.arm.com/documentation/SDEN-1982442/1700/?lang=en * Neoverse-V2 SDEN v9.0, erratum 3324336 https://developer.arm.com/documentation/SDEN-2332927/900/?lang=en Note that due to shared design lineage, some CPUs share the same erratum number. Add these to the existing mitigation under CONFIG_ARM64_ERRATUM_3194386. As listing all of the erratum IDs in the runtime description would be unwieldy, this is reduced to: "SSBS not fully self-synchronizing" ... matching the description of the errata in all of the SDENs. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240603111812.1514101-6-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [ Mark: fix conflicts in silicon-errata.rst ] Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Mark Rutland
Greg Kroah-Hartman
parent
771746afa0
commit
b9bf53354e
3 changed files with 30 additions and 2 deletions
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@ -127,14 +127,24 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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@ -147,6 +157,10 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | N/A |
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@ -1069,12 +1069,19 @@ config ARM64_ERRATUM_3117295
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If unsure, say Y.
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config ARM64_ERRATUM_3194386
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bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
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bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
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default y
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help
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This option adds the workaround for the following errata:
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* ARM Cortex-A710 erratam 3324338
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* ARM Cortex-A720 erratum 3456091
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* ARM Cortex-X2 erratum 3324338
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* ARM Cortex-X3 erratum 3324335
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* ARM Cortex-X4 erratum 3194386
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* ARM Cortex-X925 erratum 3324334
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* ARM Neoverse N2 erratum 3324339
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* ARM Neoverse V2 erratum 3324336
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* ARM Neoverse-V3 erratum 3312417
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On affected cores "MSR SSBS, #0" instructions may not affect
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@ -450,8 +450,15 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_3194386
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static const struct midr_range erratum_spec_ssbs_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
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{}
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};
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#endif
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@ -756,7 +763,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_3194386
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{
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.desc = "ARM errata 3194386, 3312417",
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.desc = "SSBS not fully self-synchronizing",
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.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
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ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
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},
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